• 한국전기전자재료학회논문지
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• 제21권5호
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• ETRI Journal
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• 제45권4호
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• pp.690-703
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• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• ETRI Journal
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• 제31권3호
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• pp.247-253
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• 2009

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.432-433
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• 2018

A new DC-DC converter circuit for LVDC(Low Voltage Direct-Current) distribution is proposed. DC-DC converter consists of two stage which are voltage balancer and converter stage. The balancing circuit adjust balance input voltage of converter circuit and compensate for unbalanced loads and short circuits. The converter circuit control the bipolar output voltage ${\pm}750V$. Simulation is carried out for this DC-DC converter system.

• Journal of Power Electronics
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• 제7권1호
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• pp.44-54
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• 2007

Ac-dc power conversion can either be done with two separate converter stages or with a single converter stage. Two-stage ac-dc converters, however, can be costly and complex, while the performance of single-stage converters is compromised due to a reduced number of components. Several researchers have therefore proposed adding some sort of auxiliary circuit consisting of a second switch and some passive elements to single-stage converters to improve their performance. Although these modified single-stage converters may have two converters, they are not two-stage converters as they do not have two separate and independently controlled converters that are always operating to convert power from one form to another. In this paper, the operation of ac-dc single-stage converters is first reviewed and their strengths and weaknesses are noted. The operation of several modified single-stage converters, including one proposed by the authors, is then discussed, and the paper concludes by presenting experimental results that confirm the feasibility of the proposed converter.

• 전력전자학회논문지
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• 제21권6호
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• pp.514-524
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• 2016

This work suggests a study on 5 kW plasma power supply design and reactor capacitance estimation algorithm for a wide range of linear output control to operate a plasma reactor. The suggested study is designed to use a two-stage circuit and control the full-bridge circuit of the two-stage circuit using the buck converter output voltage of the single-stage circuit. The switching frequency of the full-bridge circuit is designed to operate through high-frequency switching and obtain maximum output using LC parallel resonance. Soft switching technique(ZVS) is used to reduce the loss caused by high-frequency switching, and duty control of the buck converter is applied to control a wide range of linear output. The internal capacitance of the reactor cannot easily be extracted, and thus, the reactor cannot be operated in an optimized resonant state. To address this issue, this work designs the internal capacitance of the reactor such that estimations can be performed with the developed reactor capacitance estimation algorithm applied to the internal capacitance of the reactor. A 5 kW plasma power supply is designed for a wide range of linear output control, and the validity of the study on the reactor capacitance estimation algorithm is verified.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권2호
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• pp.85-92
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• 2000

30 kVA rotating-field type Super-Conducting Generator is built and tested with intensive FE(Finite Element) analysis. The generator is driven by VVVF inverter-fed induction motor. Open Circuit Characteristic(OCC) and Short Circuit Characteristic(SCC) are presented in this paper. Also, the test result under the light load(up to 3.6 kW) are given. From the design stage, 2-D FE analysis coupled with the external circuit has been performed. The external circuit includes the end winding resistance and reactance as well as two dampers. When compared with the test data, the FE analysis results show a very good agreement.

• 전자공학회논문지B
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• 제30B권5호
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• pp.10-17
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• 1993

This paper suggests a new addition algorithm. A circuit to implement the algorithm and the result of its performance evaluation are presented. The basic idea of the algorithm is that to obtain the sum of two operands, two operands bits are exclusive-ORed and then the result is inverted by the carry from the previous stage. An unique carry prediction method minimizes carry propagation. The proposed circuit has a very simple and regular structure compared with CLA (carry lookahead adder). It also requires less gates for the implementation about 50% and operates faster.

• 전자공학회논문지A
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• 제28A권1호
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• pp.46-51
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• 1991

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.