• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.986-989
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• 2002

This paper proposes a new single stage power factor correction (PFC) full bridge converter which operates at continuous conduction mode(CCM). The proposed single stage PFC consists of typical zero voltage switching(ZVS) full bridge DC/DC converter, two transformer auxiliary windings, and two small inductors, and two diodes. Neither additional active switch nor any control circuit are added for PFC resulting in very low cost. The proposed converter provides input power factor correction with CCM control and tight output voltage regulation. All switching devices are operated under ZVS with minimum voltage stress. Operation principle and analysis are explained and verified with computer simulation and experimental results on a 1.2kW, 100kHz prototype.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.385-387
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• 1996

A novel two stage soft-switching ac-to-dc convener with power factor correction is proposed. The proposed convener provides zero-voltage-switching (ZVS) condition to main switch of boost pre-regulator without auxiliary switch. Comparing to the conventional two stage approach(ZVS-PWM boost rectifier followed by off-line ZVS dc-dc step down converter), the proposed approach is simple and reducing EMI noise problem. A new simple DC-linked energy feedback circuit provides zero-voltage-switching condition to boost pre-regulator without imposing additional voltage and current stresses and loss of PWM capability. Operational principle, analysis, control of the proposed converter together with the simulation results of 1KW prototype are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.304-308
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• 2003

In this paper, two-stage low noise amplifier(LNA) for 24GHz is designed and fabricated using NE450284C HJ-FET of NEC CO. In order to get noise figure and input VSWR to be wanted, it is considered input VSWR and noise figure simultaneously in matching-circuit designing. The fabricated two-stage low noise amplifier has the gain of 16.6dB, input VSWR of 1.6, and output VSWR under 1.5.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1069-1074
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• 2016

This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.

• Journal of Power Electronics
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• v.11 no.6
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• pp.779-786
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• 2011

This paper presents a soft switching converter to achieve the functions of zero voltage switching (ZVS) turn-on for the power switches and dc voltage step-up. Two circuit modules are connected in parallel in order to achieve load current sharing and to reduce the size of the transformer core. An active snubber is connected between two transformers in order to absorb the energy stored in the leakage and magnetizing inductances and to limit the voltage stresses across the switches. During the commutation stage of the two complementary switches, the output capacitance of the two switches and the leakage inductance of the transformers are resonant. Thus, the power switches can be turned on under ZVS. No output filter inductor is used in the proposed converter and the voltage stresses of the output diodes is clamped to the output voltage. The circuit configuration, the operation principles and the design considerations are presented. Finally, laboratory experiments with a 340W prototype, verifying the effectiveness of the proposed converter, are described.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Journal of Magnetics
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• v.20 no.3
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• pp.322-329
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• 2015

This paper presents a new overlapped coilgun configuration to launch medium weight projectiles. The proposed configuration consists of a two-stage coilgun with overlapped coil covers with spacing between them. The theoretical operation of a multi-stage coilgun is introduced, and a transient simulation was conducted for projectile motion through the launcher by using a commercial transient finite element software, ANSOFT MAXWELL. The excitation circuit design for each coilgun is reported, and the results indicate that the overlapped configuration increased the exit velocity relative to a non-overlapped configuration. Different configurations in terms of the optimum length and switching time were attempted for the proposed structure, and all of these cases exhibited an increase in the exit velocity. The exit velocity tends to increase by 27.2% relative to that of a non-overlapped coilgun of the same length.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.694-700
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• 1998

A novel zero-voltage-transition (ZVT) isolated PWM boost converter for single stage power factor correction (PFC) is presented to improve the performance of the previously presented ZVT converter[8]. A simple auxiliary circuit which includes only one active switch provides zero-voltage-switching (ZVS) condition to all semiconductor devices. (Two active switches are required for the previous ZVT converter) This leads to reduced cost and simplified control circuit comparing to the previous ZVT converter. The ZVS is achieved for wide line and load ranges with minimum device voltage and current stresses. Operation principle, control strategy and features of the proposed converter are presented and verified by the experimental results from a 1.5 kW, 100 KHz laboratory prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.165-170
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• 2002

In order to solve the problem of system efficiency reduced on account of two stage power conversion, we propose a series resonant full bridge Inverter circuit for battery-fed microwave oven. This circuit has both a compact size and a light weight comparing with the conventional HVT(High Voltage Transformer) method. Also, it may be adjusted power levels of the microwave oven by a frequency control. In this paper, operational principles are explained in detail in order to understand the circuit operation. Also, a proto-type Inverter circuit with 1[kW] Power consumption is built and tested for verifying the operation.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.