• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.233-238
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• 2018

This paper proposes a seamless MPPT operation mode transfer method of photovoltaic system. The photovoltaic system consists of a DC-DC boost converter, a DC-Link, and a 3-level neutral point clamp (NPC) type inverter. The PV voltage fluctuates due to the output characteristics of the solar pane1 depending on the irradiation amount and the temperature. The photovoltaic system requires seamless MPPT mode transfer method that the discontinuity does not occur in order to supply the stable power to system without affecting the fluctuation of the PV voltage. MPPT operation is divided into two modes by the voltage reference. Under the condition that the PV voltage is below 650V, the DC-DC boost converter performs MPPT through duty control based on perturb & observe (P&O) method, and the inverter conducts DC-link voltage and grid current controls in synchronous reference frame. On the other hand, when the PV voltage exceeds above 650V, inverter performs MPPT in accordance with the variation of DC-link voltage control while the converter stops operating. Two MPPT operation modes is smoothly transferred through the proposed method that DC-link voltage or grid current commands are appropriately adjusted from the certain criteria. The feasibility of the MPPT operation mode transfer method is verified using a 10kW solar photovoltaic system, experimental results have good performances that the fluctuation of PV current is reduced to 100%.

• Journal of Power Electronics
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• v.15 no.1
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• pp.190-201
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• 2015

This paper uses the switching function approach to present a simple state model of the Vienna-type rectifier. The approach introduces the relationship between the DC-link neutral point voltage and the AC side phase currents. A novel direct power control (DPC) strategy, which is based on the sliding mode control (SMC) for Vienna I rectifiers, is developed using the proposed power model in the stationary ${\alpha}-{\beta}$ reference frames. The SMC-based DPC methodology directly regulates instantaneous active and reactive powers without transforming to a synchronous rotating coordinate reference frame or a tracking phase angle of grid voltage. Moreover, the required rectifier control voltages are directly calculated by utilizing the non-linear SMC scheme. Theoretically, active and reactive power flows are controlled without ripple or cross coupling. Furthermore, the fixed-switching frequency is obtained by employing the simplified space vector modulation (SVM). SVM solves the complicated designing problem of the AC harmonic filter. The simplified SVM is based on the simplification of the space vector diagram of a three-level converter into that of a two-level converter. The dwelling time calculation and switching sequence selection are easily implemented like those in the conventional two-level rectifier. Replacing the current control loops with power control loops simplifies the system design and enhances the transient performance. The simulation models in MATLAB/Simulink and the digital signal processor-controlled 1.5 kW Vienna-type rectifier are used to verify the fast responses and robustness of the proposed control scheme.

• Advances in Energy Research
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• v.2 no.1
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• pp.47-59
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• 2014

Back-to-back STATCOM configuration is an extension of STATCOM in which the reactive power at two-sides and the real power flow through the DC link can be controlled concurrently and independently. This flexible operation brings many advantages to the micro-grids, distributed generation based systems, and deregulated power systems. In this paper, the dynamic control characteristics of the back-to-back STATCOM is investigated by simulating the detailed converter-level model of the converters in PSCAD. Various case studies in a single-machine test system are studied to present that the real power control feature of the BtB-STATCOM, even with a simple controller design, can enhance the transient stability of the machine under different fault scenarios.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1945-1954
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• 2017

In recent years, several LCL filter design methods for different converter topologies have been published, many of which use analytical expressions to calculate the ideal converter AC voltage harmonic spectrum. This paper presents the LCL filter design methodology but the focus is on presentation and validation of the non-iterative filter design method for a grid-connected three-phase two-level PWM-VSC. The developed method can be adapted for different converter topologies and PWM algorithms. Furthermore, as a starting point for the design procedure, only the range of PWM carrier frequencies is required instead of an exact value. System nonlinearities, usually omitted from analysis have a significant influence on VSC AC voltage harmonic spectrum. In order to achieve better accuracy of the proposed procedure, the system nonlinear model is incorporated into the method. Optimal filter parameters are determined using the novel cost function based on higher frequency losses of the filter. An example of LCL filter design for a 40 kVA grid-connected PWM-VSC has been presented. Obtained results have been used to construct the corresponding laboratory setup and measurements have been performed to verify the proposed method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.565-566
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• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.86-88
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• 2018

The three level(3L) neutral point clamped (NPC) voltage source converter (VSC) topology is widely used for grid interface in high power wind energy due to its superior performance as compared to the two level(2L) VS. However, one of the major drawbacks of this topology is the unequal dispersion of loss and therefore the junction temperature among the power devices. The 3L ANPC topology derived from the NPC topology was proposed to resolve this drawback of unequal loss profile of 3L NPC. The 3L ANPC can work under various switching strategies. In this paper a comparative study of the various switching strategies of 3L ANPC using the recently developed 10kV IGCTs which has the capability to raise the current and voltage rating of the wind turbines is carried out. The comparison is performed using ABB make 10kV IGCT 5SHY17L9000 and PLECs simulations.