• 한국자동차공학회논문집
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• 제1권1호
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• pp.140-148
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• 1993

When a large automobile sheet metal part is formed in a draw die, the binder wrap is first calculated to predict the initial punch contact location for avoiding wrinkles and severe stretching of its thin blank sheet. Since the boundary of a pseudo blank in calculating a binder wrap by means of a geometrically nonlinear finite element method is unknown in advance, an iteration method is generally used. This paper presents an effective iteration method for correction of the pseudo blank in a binder wrap calculation. For the performance test, two examples are adopted. The calculated results for both examples show the good convergence which wasted solutions are obtained in the second iteration step.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 추계학술대회논문집A
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• pp.459-464
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• 2001

The main object of this study is to develop a reliable FEM simulation technique for the analysis of Steel D&I Can bodymaking process using ABAQUS software. The body making process includes drawing, redrawing, 3 step ironing, doming. The newly developed FEM code in this research is based on the previous research achievement of POSCO for the drawing, redrawing and ironing process. The analysis is performed using two dimensional axisymmetric elements to analyze the punch force, the height of can, the distribution of residual stress and strain. The effect of blank thickness, gap of ironing die is also analyzed.

• 한국공작기계학회논문집
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• 제16권5호
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• pp.166-171
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• 2007

In this paper Research development about a micro metal forming manufacturing system has been developed. A micro forming system has been achieved in Japan and it's developed micro press is limited to single forming process. To coincide with the purpose to be more practical, research and development is necessary about the press which the multi forming process is possible. We set the development of the equipment including micro deep drawing, micro punching and micro restriking process to the goal. To achieve this goal, we set the application product to a micro thin foil valve which is used in the micro pump module. The compound die set has been designed and manufactured to make two step process. The material of thin foil valve is SUS-304 and its thickness is 50$\mu$m. We can get a good forming results from micro punching experiments in this paper.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2000년도 춘계학술대회논문집
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• pp.159-162
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• 2000

Wrinkles and shape distortions are generated during the forming of B-pillar(or center pillar) which is a component of the automobile side-frame. The stretch flanging modes at the joining part of the B-pillar and the roof-rail or the side-still give rise to forming problems when taior-welded blanks are applied to the side-frames. The authors simplified B-pillar lower part to T shaped section to investigate the forming behaviors. Three of die step locations and two of blank types were tested to show the effects of weld line locations and edge conditions on he forming of tailor welded blanks. The heights of body wrinkles and the strain distribution in the stretch flanged area were measured and compared.

• 한국해양공학회지
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• 제15권2호
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• pp.66-71
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• 2001

A sectional analysis of trunk-lid carried out by using the equilibrium approach based on the force balance together with geometric relations and plasticity theory. In computing a force balance equation, it is required to define a geometric curve approximating the shape of sheet metal at any step of deformation from the interaction between the die and the deformed sheet. The trunk-lid panel material is assumed to possess normal anisotropy and to obey Hill's new yield criterion. Deformation of each section of trunk-lid panel is simulated and composed to get the three-dimensional shape by using CAD technique. It was shown that the three-dimensional shape composition of the two-dimensional analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• Design & Manufacturing
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• 제17권3호
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• pp.1-7
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• 2023

Blow molding is a manufacturing process in which thermoplastic preforms are preheated and then pneumatically expanded within a mold to produce hollow products of various shapes. The two-step process, a type of blow molding method, requires the output of multiple infrared lamps to be adjusted individually, so the process of finding initial conditions hinders productivity. In this study, digital twin technology was applied to solve this problem. A blow molding simulation technique was established and simulation-based metadata was generated. A response surface ROM (Reduced Order Model) was built using the generated metadata. Then, a dynamic ROM was constructed using the results of 3D heat transfer analysis. Through this, users can quickly check the product wall thickness uniformity according to changes in the control value of the heating lamp for products of various shapes, and at the same time, check the temperature distribution of the preform in real time.

• 소성∙가공
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• 제9권3호
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• pp.233-241
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• 2000

It is well known that the quality and efficiency of the design of metal forming processes can be significantly improved with the aid of effective numerical simulations. In the present study, a two-and three-dimensional finite element simulation system, CAMP form, was developed for the analysis of metal forming processes in the PC environment. It is composed of a solver based on the thermo-rigid-viscoplastic approach and graphic user interface (GUI) based pre-and post-processors to be used for the effective description of forming conditions and graphic display of simulation results, respectively. In particular, in the case of CAMPform 2D (two-dimensional), as the solver contains an automatic remeshing module which determines the deformation step when remeshing is required and reconstructs the new mesh system, it is possible to carry out simulations automatically without any user intervention. Also, the forming analysis considers ductile fracture of the workpiece and wear of dies for better usage of the system. In the case of CAMPform 3D, general three-dimensional problems that involve complex die geometries and require remeshing can be analyzed, but full automation of simulations has yet to be achieved. In this paper, the overall structure and computational background of CAMPform will be briefly explained and analysis results of several forming processes will be shown. From the current results, it is construed that CAMPform can be used in providing useful information to assist the design of forming processes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.