• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1050-1060
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• 1994

This paper is a study on the computer simulation of the characteristics of the superconducting fault current limiter. Input variable parameters are apparent power, load resistance value, line resistance value and so on. Initial fault current 2 times larger than the trigger current is required to reduce the switching time of SFCL. The propagation velocity increases abruptly, the transport current is several times larger than the ciritical current. In this paper, the switching time is calculated to be 323$\mu$ sec, and the initial fault current is 19 times larger than the critical current. Because the trigger coils are bifilar winding, they have little impedance in superconducting state. After fault occurred, the limiting coil acts as a superconducting reactor and the trigger coils quench at a critical current. Without the SFCL in the circuit, fault current after the load impedence is shorted might be increased to 1100A. The fault current is, therefore, successfully limited by the superconducting limiting coil to 100A determined by the coil inductance.

• Journal of Power Electronics
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• v.12 no.6
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• pp.974-981
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• 2012

A FPGA based delta modulated single phase matrix converter has been developed that may be used in both cyclo-converters and cyclo-inverters. This converter is ideal for variable speed electrical drives, induction heating, fluorescent lighting, ballasts and high frequency power supplies. The peripheral input-output and FPGA interfacing have been developed through Xilinx 9.2i, to generate delta modulated trigger pulses for the converter. The controller has been relieved of the time consuming computational task of PWM signal generation by implementing the method of trigger pulse generation in a FPGA by using Hardware Description Language VHDL in Xilinx. The trigger circuit has been tested qualitatively by observing various waveforms on an oscilloscope. The operation of the proposed system has been found to be satisfactory.

• 전기의세계
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• v.28 no.9
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• pp.51-59
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• 1979

The forming and design method of D.C thyristor chopper circuit for DC Series motor control is suggested, ard the computation method of thyristor commutaing element's, value which makes it all the more important, is possible. Also the trigger circuit was dealt with. In this paper, in order to control the duty cycle, the duty time is kept on constancy and variable chopping frequency was adopted. By above mentioned circuit design method, the D.C thyristor chopper circuit was implemented and tested. In this circuit, the result of D.C motor control was good and reliable. The relation between the $K_{d}$ and the ratio of input-output current, or the characteristic of speed was varied lineary at the range 0.1 ~ 0.9 of duty cycle. This confirms the fact that D.C to D.C power conversion which is the merit of chopper control is operated most likely a transformer.ormer.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2067-2069
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• 1998

A prototype semiconductor switch for the command resonant charging system has been developed for a line type modulator, which charges parallel pulse forming network(PFN) up to voltage of 5 kV at repetition rates of 60 Hz. A phase controlled power supply provides charging of the 4.7 ${\mu}s$ filter capacitor bank to voltage up to 5 kV. A solid state module of series stack array of sixe matched SCRs(1.6 kV, 50 A) is used as a command charging switch to initiate the resonant charging cycle. Both resistive and RC snubber network are used across each stage of the switch assembly in order to ensure proper voltage division during both steady state and transient condition. A master trigger signal is generated to trigger circuits which are transmitted through pulse transformer to each of the 6 series switch stages. A pulse transformer is required for high voltage trigger or power isolation. This paper will discuss trigger method, protection scheme, circuit simulation, and test result.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1683-1693
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• 2017

This paper analyses the harmonic pollution to power grids caused by thyristor-controlled devices. It also formulates a mathematic derivation for the voltage spikes in thyristor-controlled branches to explain the harmonic and EMI derived from the reverse-recovery characteristics of the thyristor. With an equivalent nonlinear time-varying voltage source, a detailed simulation model is established, and the periodic dynamic switching characteristic of the thyristor can be explicitly implied. The simulation results are consistent with the probed results from on-site measurements. An improved trigger system with gate-shorted circuit structure is proposed to reduce the voltage spikes that cause EMI. The experimental results indicate that a prototype with the improved trigger system can effectively suppress the voltage spikes.

• Progress in Superconductivity and Cryogenics
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• v.21 no.3
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• pp.38-42
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• 2019

To protect the power systems from fault current, the rated protective equipment should be installed. However growth of power system scale and concentration of loads caused the large fault current in power transmission system and distribution system. And capacities of installed protective equipment have been exceeded the due to increase of fault current. This increase is not temporary phenomenon but will be steadily as long as the industry develops. The power system need a counter measurement for safety, so superconducting fault current limiter (SFCL) has been received attention as an effective solutions to reduce the fault current. For the above reasons various type SFCL is studied recently. In this paper, the operational characteristics and power burden of trigger type SFCL is studied. The trigger type SFCL has been used for real system research in many countries. And another trigger type SFCL (double quench trigger type SFCL) is also studied. For this paper, short circuit test is performed.

• Journal of IKEEE
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• v.18 no.1
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• pp.25-30
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• 2014

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.10a
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• pp.327-329
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• 2009

A first short stoke current which has a 10/350 ${\mu}s$ waveform is able to be generated by using the crowbar switch in R-L-C circuit. In this paper, a peaking circuit has been applied to make crowbar switch. Operate effective for generating 10/350 ${\mu}s$ waveform. According to simulation with PSpice, we have found that some value of inductance were more effective to trigger a crowbar switch. As a result of experimental test using crowbar switch with peaking circuit, the success rate of triggering crowbar switch is higher than the normal crowbar switch without peaking circuit.