• 한국펄프종이공학회:학술대회논문집
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• 한국펄프종이공학회 2003년도 춘계학술발표논문집
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• pp.70-79
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• 2003

Paper coating can give smoothness surface and good printability to uncoated paper. Macro roughness of base paper would be decreasing its groove and grit in view of side. Nevertheless its improving effect for paper, some kind of problem is showing in the fine coated paper. Especially, back trap mottle is one of serious problems in printing with fine coated paper. Printers can not adjust conditions to overcome the problem. Also large amounts of paper can be rejected. There are many factors that influence back trap mottle. However it is not clear what the important parameters are in back trap mottle. Back trap mottle has some relationship with ink setting but good guidelines are not clear. Back trap mottle has been linked to non-uniform ink setting. We do not know how much variation in setting we can tolerate. Other mottle issues such as micro-picking and ink refusal are still common. This paper was prepared to identify correlation with ink setting and delta ink density obtained from experiment and then tried to find out some relationships with ink setting and back trap mottle. Basically fine calcium carbonate and ciay was used for main components and coarse calcium carbonate was mixed in two fine pigments to change its porosity and ink acceptance. Micro ink tack force at KRK printing tester was adapted to measure ink setting rate. KRK units were used for back trap mottle simulation and two printed samples were prepared to check delta ink density. Clay base coating has more fast ink setting time than calcium carbonate's though smoothness of clay was better than calcium carbonate. It could be explained by that clay has finer pore in its coating than calcium carbonate. DID(delta ink density) has shown a good correlation with ink setting time from micro ink tack. The total pore volume of coating layer did not match with ink setting and DID. From the results we might conclude coating that has fine pore size around 0.05 ${\mu}m$ can be exposed to high possibility of back trap mottle.

• 한국결정성장학회지
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• 제12권6호
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• pp.304-310
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• 2002

실리콘 기판 위의 초기 산화막을 NO 열처리 및 재산화 공정방법으로 성장한 재산화된 질화산화막을 게이트 유전막으로 사용한 새로운 전하트랠형 기억소자로의 응용가능성과 계면트랩특성을 조사하였다. 0.35$\mu$m CMOS 공정기술을 사용하여 게이트 유전막은 초기산화막을 $800^{\circ}C$에서 습식 산화하였다 전하트랩영역인 질화막 층을 형성하기 위해 $800^{\circ}C$에서 30분간 NO 열처리를 한 후 터널 산화막을 만들기 위해 $850^{\circ}C$에서 습식 산화방법으로 재산화하였다. 프로그램은 11 V, 500$\mu$s으로 소거는 -l3 V, 1 ms의 조건에서 프로그래밍이 가능하였으며, 최대 기억창은 2.28 V이었다. 또한 11 V, 1 ms와 -l3 V, 1 ms로 프로그램과 소거시 각각 20년 이상과 28시간의 기억유지특성을 보였으며 $3 \times 10^3$회 정도의 전기적 내구성을 나타내었다. 단일접합 전하펌핑 방법으로 소자의 계면트랩 밀도와 기억트랩 밀도의 공간적 분포를 구하였다. 초기상태에서 채널 중심 부근의 계면트랩 및 기억트랩 밀도는 각각 $4.5 \times 10^{10}/{cm}^2$ 와 $3.7\times 10^{1R}/{cm}^3$ 이었다. $1 \times 10^3$프로그램/소거 반복 후, 계면트랩은 $2.3\times 10^{12}/{cm}^2$으로 증가하였으며, 기억트랩에 기억된 전하량은 감소하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2005년도 춘계학술발표대회 및 제8회 신소재 심포지엄 논문개요집
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• pp.53-53
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• 2005

• 한국응용곤충학회지
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• 제34권4호
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• pp.391-405
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• 1995

수원 지방에 서식하는 바퀴의 종류와 상대밀도를 조사하기 위하여 수원 시내 7개 다른 서식처, 여관, 다방, 중식 음식점, 한식 음식점, 개인 병원, 아파트, 그리고 단독주택을 선정하여 끈끈이 트랩에 의한 바퀴의 채집과 서식처별 상대밀도조사를 1994년 2월부터 11월까지 실시하였다. 설치된 3,039개의 트랩 중 1,435개의 트랩에서 한마리 이상의 바퀴가 채집된 Positive Trap Rate(양성 트랩율)은 47.22%였다. 중식 음식점에서의 양성트랩율은 72.67%이었고, 채집된 바퀴의 수가 전 채집개체의 48.84%로 바퀴오염이 가장 심한 빈도를 나타내었다. 그에 비하여 한식 음식점, 아파트, 단독주택, 다방, 여관, 그리고 병원에서는 보다 조금 낮거나 매우 낮은 60.6%, 58.61%, 52.22%, 38.67%, 24.88% 그리고 17.54%로 각각 나타났다. B. germanica는 전 채집개체 수의 97.36%로 가장 높은 밀도를 나타내었으며, 55.01 개체/트랩/주의 평균 밀도를 보였다. 반면, 다른 종인 P. japonica, P. americana와 P. fuliginosa는 이보다 훨씬 낮은 2.35%, 0.14%, 0.14%를 보였다. 7개의 서로 다른 서식처에서 개체군 밀도를 조사해 본 결과 중식 음식점과 한식 음식점에서 20.56과 8.31개체/트랩/주라는 보다 높은 개체군 밀도가 관찰되었다. 그에 비해 아파트, 다방과 단독주택에서는 5.33, 3.79와 3.53 개체/트랩/주의 중간 범위 밀도가 조사되었고, 비교적 낮은 밀도가 병원(0.18 개체/트랩.주)과 여관(1.00 개체/트랩/주)으로 부터 관찰되었다.

• 한국전기전자재료학회논문지
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• 제24권11호
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.383-384
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• 2008

In this paper, we extract interface trap density with treatment of gate dielectric of OTFT's. Interface trap densities in this paper were extracted from transfer curves. We obtained interface trap densities in pentacene / PVP interface Non-treated device has $1.4{\times}10^{12}cm^{-2}eV^{-1}$ Dit and treated device has $1.1{\times}10^{12}cm^{-2}eV^{-1}$ Dit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• 센서학회지
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• 제27권3호
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• 대한전자공학회논문지
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• 제24권4호
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• pp.625-630
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• 1987

Thermal evaporated SiO rf sputtered SiO2 thin films were most widely used to the gate oxide of TFTs. In this paper, the difference of trap density and distribution between SiO2 and SiO2 film were studied. TFTs using SiO and SiO2 thin film for the gate oxide were fabricated. The output characteirstics of TFTs and the time dpendencd of the leakage current were measured. Models of the carrier transport and carrier trapping in TFT were proposed. The trap density was obtained by substituting measured value for the equation derived from the proposed model. It was found that rf sputtered SiO2 had more traps at interface than thermal evaporated SiO.