• Proceedings of the Korea Technical Association of the Pulp and Paper Industry Conference
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• 2003.04a
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• pp.70-79
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• 2003

Paper coating can give smoothness surface and good printability to uncoated paper. Macro roughness of base paper would be decreasing its groove and grit in view of side. Nevertheless its improving effect for paper, some kind of problem is showing in the fine coated paper. Especially, back trap mottle is one of serious problems in printing with fine coated paper. Printers can not adjust conditions to overcome the problem. Also large amounts of paper can be rejected. There are many factors that influence back trap mottle. However it is not clear what the important parameters are in back trap mottle. Back trap mottle has some relationship with ink setting but good guidelines are not clear. Back trap mottle has been linked to non-uniform ink setting. We do not know how much variation in setting we can tolerate. Other mottle issues such as micro-picking and ink refusal are still common. This paper was prepared to identify correlation with ink setting and delta ink density obtained from experiment and then tried to find out some relationships with ink setting and back trap mottle. Basically fine calcium carbonate and ciay was used for main components and coarse calcium carbonate was mixed in two fine pigments to change its porosity and ink acceptance. Micro ink tack force at KRK printing tester was adapted to measure ink setting rate. KRK units were used for back trap mottle simulation and two printed samples were prepared to check delta ink density. Clay base coating has more fast ink setting time than calcium carbonate's though smoothness of clay was better than calcium carbonate. It could be explained by that clay has finer pore in its coating than calcium carbonate. DID(delta ink density) has shown a good correlation with ink setting time from micro ink tack. The total pore volume of coating layer did not match with ink setting and DID. From the results we might conclude coating that has fine pore size around 0.05 ${\mu}m$ can be exposed to high possibility of back trap mottle.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.53-53
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• 2005

• Korean journal of applied entomology
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• v.34 no.4
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• pp.391-405
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• 1995

Cockroach survey on the relative density from 7 different habitats including hotel-ins, tea-rooms restaurants, hospitals, apartments, and resident hoses were conducted in 3 District(Ku) areas in Suwon city during the period of February through October, 1994. of a total of 3.039 trap sets, Cockroaches were collected from 1,435 traps, comprised of a 47.22% positive trap-rate. Chinese restaurants were shown to be the highest positive trap-rate of 72.67% of the total while the other habitats such as Korean restaurants, apartments, resident hoses, tea-rooms, hotel-inns, and hospitals were 60.67%, 58.61%, 52.22%, 38.67%, 24.88%, and 17.54%, respectively. Blattella germanica was shown to be the highest population density of 55.01 individuals/trap/week comprised of 97.36% of the total during survey period whereas the other 3 species, Periplaneta japonica, P. americana, and P. fuliginosa constituted in lesser extent of 2.35%, 0.14%, respectively. Of a total of 7 different cockroach breeding habitats, higher population density per trap/week was from restaurants with averages of 20.56 and 8.31 cockroaches from Chinese and Koran restaurants, respectively. An intermediate extent of density was observed from apartments, tea rooms and resident houses with 5.33, 3.79 and 3.53 individuals, respectively. Lower relative densities of cockroaches were observed from hospitals and hotel-inns with averages of 0.18 and 1.00 individuals per trap/week, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.383-384
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• 2008

In this paper, we extract interface trap density with treatment of gate dielectric of OTFT's. Interface trap densities in this paper were extracted from transfer curves. We obtained interface trap densities in pentacene / PVP interface Non-treated device has $1.4{\times}10^{12}cm^{-2}eV^{-1}$ Dit and treated device has $1.1{\times}10^{12}cm^{-2}eV^{-1}$ Dit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• Journal of Sensor Science and Technology
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• v.27 no.3
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.625-630
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• 1987

Thermal evaporated SiO rf sputtered SiO2 thin films were most widely used to the gate oxide of TFTs. In this paper, the difference of trap density and distribution between SiO2 and SiO2 film were studied. TFTs using SiO and SiO2 thin film for the gate oxide were fabricated. The output characteirstics of TFTs and the time dpendencd of the leakage current were measured. Models of the carrier transport and carrier trapping in TFT were proposed. The trap density was obtained by substituting measured value for the equation derived from the proposed model. It was found that rf sputtered SiO2 had more traps at interface than thermal evaporated SiO.