• 전기전자학회논문지
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• 제11권3호
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• pp.122-128
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• 2007

Sinusoidal voltage-controlled oscillators (VCOs) based on Colpitts and Hartley oscillators are presented. They consist of a LC parallel-tuned circuit connected in a negative-feedback loop with an OTA-R amplifier and two diode limiters, where the inductor is simulated one realized with temperature-stable linear operational transconductance amplifiers (OTAs) and a grounded capacitor. Prototype VCOs are built with discrete components. The Colpitts VCO exhibits less than 1% nonlinearity in its current-to-frequency transfer characteristic from 4.2 to 21.7 MHz and ${\pm}$95 ppm/$^{\circ}C$ temperature drift of frequency over 0 to $70^{\circ}C$. The total harmonic distortion (THD) is as low as 2.92% with a peak-to-peak amplitude of 0.7 V for a frequency-tuning range of 10.8-32 MHz. The Hartley VCO has the temperature drift and THD of two times higher than those of the Colpitts VCO.

• 대한전자공학회논문지
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• 제25권7호
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.54-62
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• 2003

OTA를 이용한 전류-제어 인덕터를 시뮬레이션하기 위한 체계적인 합성 과정을 기술했다. 그 합성 과정을 통해 세 개의 시뮬레이티드 인덕터를 설계했고, 그 중에서 두 개는 새롭게 설계된 것이다. 또한, 이 합성 과정을 전류-제어 FDNR 설계에 적용했다. 설계된 회로들의 동작 원리를 제시했고, 실험을 통해 설계 이론의 타당성을 증명했다. FDNR을 전류-제어 대역-통과 여파기에 응용한 예도 제시했다.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권1호
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• pp.19-22
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• 1999

N-doped and low-hydrogenated DLC thin films were coated on the Mo-tip FEAs in order to improve the field emission performance and their electrical properties were evaluated. The fabricated devices showed improved field emission performance in terms of turn-on voltage, emission current and current fluctuation. This result might be caused both by the shift of Fermi level toward conduction band by N-doping and by the inherent stability of DLC material. Furthermore, the transconductance of the DLC-coated Mo-tip FEA and electrical conductivity and optical band-gap of the deposited DLC films were investigated.

• 대한전자공학회논문지
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• 제27권2호
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• pp.98-104
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• 1990

$P^+$형 다결정 실리콘 게이트와 n형 다결정 실리콘 게이트를 갖는 P채널 MOSFET를 제작하였다. 채널의 길이와 채널의 이온 주입 조건에 따라 SC-PMOSFET와 BC-PMOSFET의 transconductance 문턱저압저하 및 subthreshold 특성을 분석하였다. 측정된 소자의 특성으로 부터 SC-PMOSFET소자가 BC-PMOSFET 소자에 비하여 transconductance는 작으며 subthreshold 영역에서 누설전류도 작고 문턱 전압 저하및 DIBL영향이 작게 일어남을 알 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.207-210
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• 2000

This paper introduces a voltage-mode biquadratic circuit using only Operational Amplifiers (OTAs) and Operational Transconductance Amplifiers (OTAs). The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. Some examples are given together with simulated results by PSpice. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.486-489
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• 2002

본 논문에서는 50nm 이하의 double gate MOSFET의 특성을 조사하였다. 1.5V의 main gate 전압과 3V의 side gate 전압이 인가될 때 I-V 특성으로부터 IDsat=510$\mu$A/$\mu\textrm{m}$을 얻을 수 있었다. 이때, 전달 컨덕턴스는 111$\mu$A/V, subthreshold slope는 86mV/dec, DIBL값은 51.3mV이다. 그밖에 TCAD tool이 소자 시뮬레이터로서 적합함을 나타내었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.490-493
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• 2002

본 논문에서는 main gate와 side gate를 갖는 double gate MOSFET의 side gate 길이와 side gate 전압에 대한 최적의 값을 조사하였다. main gate 50nm에서 각각의 side gate 길이에 대한 최적의 side gate 전압은 대략 3V이다. 또한, main gate 길이에 대한 최적의 side gate 길이는 대략 70nm이다. 이때, side gate 길이에 대한 전달 컨덕턴스 및 subthreshold slope에 대한 값들을 나타내었다. 이때 소자의 특성 분석을 위해 ISE-TCAD를 사용하여 시뮬레이션 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.