• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.333-336
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• 2002

An alternative CMOS implementation of a multi-output four-terminal floating nullor (FTFN) with constant-g$_{m}$ rall-to-rail input stage is proposed. This presented circuit is based on the advantages of a complementary transconductance amplifier and class AB dual translinear cell circuit that comes up with wide bandwidth. The constant-g$_{m}$ characteristic is controlled by the maximum-current selection circuits, maintaining the smooth response over the change of input common mode voltage. The circuit performances are confirmed through HSPICE simulations. A current-mode multifunction filter is used to exhibit the potentiality of this proposed scheme.eme.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.88-91
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• 2000

An MMIC oscillator operating at the 24.55 GHz has been designed using 0.2 ${\mu}{\textrm}{m}$AlGaAs/InGaAs/GaAs Pseudomorphic HEMT technology. The active device used in the oscillator design has a 0.2 ${\mu}{\textrm}{m}$ gate length PHEMT with 4$\times$80 ${\mu}{\textrm}{m}$ gate width. We obtained 4.08 dB of S$_{21}$ gain and 317 mS/mm of transconductance, and extrapolated unit current gain cut-off frequency (f$_{T}$) and maximum oscillation frequency (fmax) were 62 GHz and 120 GHz, respectively. The circuit are based on a series feedback and negative resistance topology. Microstrip line open stub is used to terminating. The oscillator circuits has designed for delivering maximum power to load and conjugated matching. The simulated small signal negative resistance was 50 Ω. We obtained 1.002 of loop gain and 0.0005$^{\circ}$angle from the simulation by HP libra 6.1. The layout for oscillator is 1.2$\times$1.8 $\textrm{mm}^2$.>.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.35-40
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• 1997

To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.579-582
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• 2005

In this study, the electrical characteristic of asymmetric high voltage MOSFET (AHVMOSFET) for display IC was investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length, and gate oxide thickness ($175{\AA}$, $350{\AA}$). In high temperature condition, drain current decreased over 30% and max transconductance deceased over 40%, and specific on-resistance increased over 30% in comparison with room temperature.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.897-900
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• 2005

RF linearity of double-gate MOSFETs is investigated using accurate two-dimensional simulations. The linearity has been analyzed using the Talyor series. Transconductance is dominant nonlinear source of CMOS. It is shown that DGMOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration. The minimum $P_{IP3}$ data are compared in each case. It is shown that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration..

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.7-9
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• 2011

본 논문은 LED 백라이트 구동을 위한 전력변환 제어기 설계 및 동특성에 대해 설명한다. 또한 근래 산업계에서 널리 사용하는 operational transconductance amplifier(OTA)와 operational amplifier(op-amp)의 상관관계를 분석하여 각각의 소자를 이용한 최적 제어기를 설계하였다. 설계와 해석을 위해 PSIM 시뮬레이션을 사용하였으며 구현한 PSIM 모델은 실험을 통하여 타당성을 증명하였다.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.549-552
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• 1998

Recently, the gate oxide damage induced by the plasma processes has been one of the most significant reliability issues as the gate oxide thickness falls below 10 nm. The process-induced damage was studied with the metal antenna test structures. In addition to the electron trapping, the hole trapping in a 10 nm thick gate oxide due to the plasma-induced charging was observed in the NMOS's with a metal antenna. The hole trapping gave rise to the decrease of the transconductance (gm) similarly to the case of the electron trapping, but to the extent much less than the electron trapping. It would be because the electrical stress that the plasma-induced charging forced to the gate oxide for the devices with the hole trapping was much smaller than for those with the electron trapping. This hypothesis was strongly supported by the measured characteristics of the Fowler-Nordheim current in the gate oxide.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.815-818
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• 1998

The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.

• 전기의세계
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• v.27 no.4
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• pp.45-51
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• 1978

A new method of realizing the field effect transistor with a sub-.mu. channel width is described. The sub-.mu. channel width is made possible by etching grooves into n$^{+}$ pn$^{[-10]}$ n$^{[-10]}$ structure and using p region at the wall for the channel region of the Metal-Oxide-Semiconductor transistor (MOST), or by diffusing two different types of impurities through the same diffusion mask and using p region at the surface for the channel region of MOST. When the drain voltage is increased at the pn$^{[-10]}$ drainjunction the depletion layer extends into the n$^{[-10]}$ region instead of into p region; this is also the secret of success to realize the sub-.mu. channel width. As the result of the experimental fabrication, a microwave MOST was obtained. The cut-off frequency was calculated to be 15.4 GHz by Linvill's power equation using the measured capacitances and transconductance.