• International Journal of Contents
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• v.5 no.2
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• pp.43-52
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• 2009

The article first presents a broad overview of the design and management for survivable network. We review the concept of network survivability, various protection and restoration schemes. Also we introduce design architectures of Quantitative model and a Survivable Ad hoc and Mesh Network Architecture. In the other side of study like these(traditional engineering approach), there is the concept of the survivable network systems based on an immune approach. There is one sample of the dynamic multi-routing algorithms in this paper.

• Journal of Information Technology Services
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• v.3 no.2
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• pp.129-140
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• 2004

Traditional information systems in the Ministry of National Defense(MND) are insufficient about interoperability between all kinds of them. Also there is no the applicable architecture framework to develop information systems. The Architecture Framework(AF) is to provide guidance for describing architectures for both warfighting operations and business operations and processes in the MND. Therefore, in this paper we propose the MND AF to develop and manage information systems in the MND.

• The Bulletin of The Korean Astronomical Society
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• v.45 no.1
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• pp.49.4-50
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• 2020

We introduce a novel method for reconstructing the projected matter distributions of galaxy clusters with weak-lensing (WL) data based on convolutional neural network (CNN). We control the noise level of the galaxy shear catalog such that it mimics the typical properties of the existing Subaru/Suprime-Cam WL observations of galaxy clusters. We find that our mass reconstruction based on multi-layered CNN with architectures of alternating convolution and trans-convolution filters significantly outperforms the traditional mass reconstruction methods.

• Journal of the Korean Institute of Rural Architecture
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• v.14 no.3
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• pp.25-32
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• 2012

Traditional folk houses in Yongdong, Gangwon province play important roles in figuring out natural, human, and social value in the past time including housing life. However, according to the introduction of electric or plumbing equipment in housing life styles, many conventional architectures have been changed by installations of new electric or plumbing equipment, convenience facilities, and etc. Therefore, this study aims to make basic data to prepare for standardized installations of the electric or plumbing equipment, and convenience facilities by surveying of the present installation status, such as electric lights, outlets, switches, wiring, pipe laying, or monitoring devices for crime, disaster prevention facilities, and home appliances etc. Additionally, this paper is related to the meaning and usage, which are connected with the electric or plumbing equipment installations of the traditional folk houses to be prepare for the proper solutions between preservations of the original form and convenient lives for residents.

• Journal of Information Processing Systems
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• v.7 no.3
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• pp.435-446
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• 2011

Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique significantly increases the verification workload on the processor resources, resulting in severe performance degradation. This paper presents a pro-active verification management approach to mitigate the verification workload to increase its performance with a minimal effect on overall reliability. An anomaly-speculation-based filter checker is proposed to guide a verification priority before the re-execution process starts. This technique is accomplished by exploiting a value similarity property, which is defined by a frequent occurrence of partially identical values. Based on the biased distribution of similarity distance measure, this paper investigates further application to exploit similar values for soft error tolerance with anomaly speculation. Extensive measurements prove that the majority of instructions produce values, which are different from the previous result value, only in a few bits. Experimental results show that the proposed scheme accelerates the processor to be 180% faster than traditional fully-fault-tolerant processor with a minimal impact on overall soft error rate.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.119-127
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• 2015

In the IoT(Internet of Things) environment, methods that user can access sensor node directly to collect sensing data or manage sensor in a gateway have a limitations. To solve this problem, cloud based sensor network architectures are proposed. In this paper, we proposed CoAP based IoT architecture that a lightweight gateway is used for data gathering instead of using a heavy traditional one and users can request sensing data through IoT applications running in the cloud environment and analyze signaling message cost. By doing so, our system can reduce message cost compared to the traditional gateway based system.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.23-36
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• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.