• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.5
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• pp.123-128
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• 2024

The tracking radar system is a system that transmits a radar signal to acquire and track a very weak signal that hits the target and returns. In addition, it is essential to apply the FPGA for high-speed preprocessing and the multi-core DSP for real-time algorithm performance to process radar signals in a short time. For the ADC, FPGA, and DSP design, the design of the power required by each is also very important. This paper describes the optimal power design of the signal processor consisting of ADC, FPGA, and DSP for radar signal processing. It explains in detail what parts are applied to each component to design the desired power. We present the finally designed circuit board.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.4
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• pp.573-577
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• 2015

In this paper, we propose a signal processing board suitable for a semi-active laser tracking to detect an optical signal generated from the laser target designator by applying an analog trigger signal, the quadrant photodetector and a high speed ADC(analog-digital converter) sampling technique. We improved the stability by applying the averaging method to minimize the measurement error of a gaussian pulse. To evaluate the performances of the proposed methods, we implemented a prototype board and performed experiments. As a result, we implemented a frequency counter with an error 14.9ns in 50ms. PRF error code has a stability of less than 1.5% compared to the NATO standard. Applying the three point averaging method to ADC sampling, the stability of 28% in X-axis and 22% in Y-axis than one point sampling was improved.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1447-1453
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• 2014

This paper proposes the new method based on the availability of three points measurement and convexity of photovoltaic (PV) curve characteristic at the maximum power point (MPP). In general, the MPP tracking (MPPT) function is the important part of all PV systems due to their power-voltage (P-V) characteristics related with weather conditions. Then, the analog-to-digital converter (ADC) and low pass filter (LPF) are required to measure the voltage and current for MPPT by the digital controller, which is used to implement the PV power conditioning system (PCS). The measurement and quantization error due to rounding or truncation in ADC and the delay of LPF might degrade the reliability of MPPT. To overcome this limitation, the proposed method is proposed while improving the performances in both steady-state and dynamic responses based on the detailed investigation of its properties for availability and convexity. The performances of proposed method are evaluated with the several case studies by the PSCAD/EMTDC$^{(R)}$ simulation. Then, the experimental results are given to verify its feasibility in real-time.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.15-21
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• 2007

In this paper, we propose a technique of a practical symbol acquisition and tracking using a low complex ADC and simple digital circuits for noncoherent asynchronous impulse-radio-based Ultra Wideband (IR-UWB) receiver based on energy detection. Compared to previous approaches of detecting an exact acquisition time that require much hardware resource, the proposed technique is to detect the target symbol by finding the symbol acquisition interval per symbol with a target symbo, thus the complexity of the complete signal processing and power consumption by ADC are reduced. To do this, we define the bit decision window (BDW) and analyze the relation between SNR, hardware resource, size of BDW and BER(Bit Error Rate). Using the results, the optimum BDW size for the minimum BER with limited hardware resource is selected. The proposed synchronization technique is verified with an aid of a simulator programmed by considering practical impulse channels.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.49-55
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• 2021

Recently, a small tracking radar requires the development of a small millimeter wave tracking radar having a high range resolution that can acquire and track a target in various environments and disable the target system with a single blow. Small millimeter wave tracking radar with high range resolution needs to implement a signal processor that can process wide bandwidth signals in real time and meet the requirements of small tracking radar. In this paper, we designed a signal processor that can perform the role and function of a signal processor for a small millimeter wave tracking radar. The signal processor for the small millimeter wave tracking radar requires the real-time processing of input signal of OOOMHz center frequency and OOOMHz bandwidth from 8 channels. In order to satisfy the requirements of the signal processor, the signal processor was designed by applying the high-performance FPGA (Field Programmable Gate Array) and ADC (Analog-to-digital converter) for pre-processing operations, such as DDC (Digital Down Converter) and FFT (Fast Fourier Transform). Finally, the signal processor of the small millimeter wave tracking radar was verified via performance test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.608-614
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• 2015

A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.132-137
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• 2003

This performance is motivated to develop a tracking antenna system for receive the satellite broadcasting signal in the coast sailing ship. Therefore, this system is made to small size, light weight and simple operation which is must to low cost system for popularization of small size ship and adaptive possibilities with useful on a ship in the coast using 1 axis Az-mount. The antenna mount structure is a compact size and easy operation to the Az-axis type which is operated by step motor. The antenna unit is a domestic made plate type of patch array and ship's moving detection is using the gyro sensor for ship's moving control. We are designed to algorithm, which walking is abreast for step track and ship's moving compensation. Ship's moving compensation is adapted to the closed loop control method by detection from gyro sensor. This system is consisted of micro processor, ADC, comparative amplifier, step motor driver, mount mechanism and algorithm. We have analysised the tracking performance of prototype on sailing ship board.