• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• 전력전자학회논문지
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• 제25권4호
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• pp.269-278
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• 2020

In this paper, two types of DC/DC converters in a hydrogen fuel cell hybrid railway vehicle system, which serve to charge high-voltage battery and supply power to an inverter for driving a driving motor, were compared and analyzed. A two-level interleaving boost converter and a three-level boost converter were compared and analyzed, and a theoretical design method was proposed to have an efficiency characteristic of over 95%. In addition, a digital controller design method considering the digital phase delay component of DSP (TMS320F28335) is presented. Finally, the validity of the theoretical design of the converter with 20kW power was verified through static and dynamic experiments respectively.

• 전기학회논문지
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• 제58권8호
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• pp.1544-1550
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• 2009

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is proposed. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy or compensating voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method that is commonly employed in the direct power conversion. Simulation and experimental results are shown to demonstrate the advantages of the new compensator and PWM strategy. A 220V, 3kVA single-phase compensator based on the digital signal processor controller is built and tested.

• Journal of Power Electronics
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• 제16권5호
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• pp.1833-1842
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• 2016

In grid-connected converter control, grid voltage feedforward is usually introduced to suppress the influence of grid voltage distortion on the converter's grid-side AC current. However, owing to the time-delay in control systems, the suppression effect of the grid voltage distortion is seriously affected. In this paper, the positive effects of the grid voltage feedforward control are analyzed in detail, and the time-delay caused by the low-pass filter (LPF) in the voltage filtering circuits and digital control are summarized. In order to reduce the time-delay effect on the performance of the feedforward control, a voltage feedforward control strategy with time-delay compensation is proposed, in which, a leading correction of the feedforward voltage is used. The optimal leading step used in this strategy is derived from analyzing the phase-frequency characteristics of a LPF and the implementation of digital control. By using the optimal leading step, the delay in the feedforward path can be further counteracted so that the performance of the feedforward control in terms of suppressing the influence of grid voltage distortion on the converter output current can be improved. The validity of the proposed method is verified through simulation and experiment results.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.35-40
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• 2005

본 논문에서는 1.6Gb/s에서 동작하는 digitally controlled phase-locked loop (DCPLL)를 제안한다. DCPLL은 일반적인 아날로그 PLL과 tracking analog-to-digital 변환기를 결합한 구조이다. 제안한 DCPLL에서는 tracking ADC의 출력이 voltage controlled oscillator (VCO)의 제어 전압을 생성한다. 일반적으로 사용되는 digital PLL (DPLL)은 digitally controlled oscillator (DCO)와 time-to-digit converter (TDC)로 구성된다 DCO와 TDC를 사용한 DPLL은 시간 스텝이 작을 수 록 jitter 특성이 향상되지만 전력소모는 커진다. 이 논문에서 제안한 DCPLL은 DPLL의 핵심요소인 DCO와 TDC를 사용하지 않았기 때문에 jitter, 면적, 전력소모 측면에서 유리하다. DCPLL은 $0.18\mu$m 4-metal CMOS공정을 이용하여 제작하였고 면적은 1mm $\times$0.35mm를 차지한다. 1.8V 단일 전원전압으로 정상동작에서는 59mW, power-down 모드에서는 $984\mu$W 전력을 소모하고 16.8ps rms jitter를 갖는다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.232-237
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• 2004

In many application of DC-DC converters, loads cannot be specified in advance, i.e., their amplitudes are suddenly changed from the zero to the maximum rating. Generally, design conditions are changed for each load and then each controller is re-designed. Then, a so-called robust DC-DC converter which can cover such extensive load changes and also input voltage changes with one controller is needed. Analog control IC is used usually for the controller of DC-DC converter. Simple integral control etc. are performed with the analog control IC. However it is difficult to retain sufficient robustness of DC-DC converter by these techniques. The authors proposed the method of designing an approximate 2-degree-of-freedom (2DOF) controller of DC-AC converter. This controller has an ability to attain sufficient robustness against extensive load and DC power supply changes. For applying this approximate 2DOF controller to DC-DC converter, it is necessary to improve the degree of approximation for better robustness. In this paper, we propose a method of designing good approximate 2DOF digital controller which makes the control bandwidth wider, and at the same time makes a variation of the output voltage very small at a sudden change of resistive load. The proposed good approximate 2DOF digital controller is actually implemented on a DSP and is connected to a DC-DC converter. Experimental studies demonstrate that this type digital controller can satisfy given specifications.

• 한국통신학회논문지
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• 제32권10C호
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• pp.1019-1024
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• 2007

본 논문에서는 무선 랜 시스템용 10비트 20MHz 파이프라인 아날로그-디지털 변환기 설계를 위해서 Verilog-A 언어를 사용하여서 모델링하였다. 변환기내 샘플 / 홀드 증폭기, 비교기, MDAC 및 오차 보정 회로 등의 구성회로들을 각각 모델링해서 모의실험 한 결과 HSPICE를 이용한 모의 실험 시간보다 1/50배로 단축되어서 시스템 모델링에 적합함을 확인하였다.

• 한국정보통신학회논문지
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• 제17권2호
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• pp.414-422
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• 2013

본 논문은 분할-커패시터 기반의 차동 디지털-아날로그 변환기 (DAC: digital-to-analog converter)를 이용하는 10-bit 10-MS/s 비동기 축차근사형 (SAR: successive approximation register) 아날로그-디지털 변환기 (ADC: analog-to-digital converter)를 제안한다. 샘플링 주파수를 증가시키기 위해 SAR 로직과 비교기는 비동기로 동작을 한다. 또한 높은 해상도를 구현하기 위해 오프셋 보정기법이 적용된 시간-도메인 비교기를 사용한다. 제안하는 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기는 0.18-${\mu}m$ CMOS 공정에서 제작되며 면적은 $140{\times}420{\mu}m^2$이다. 1.8 V의 공급전압에서 전력소모는 1.19 mW이다. 101 kHz 아날로그 입력신호에 대해 측정된 SNDR은 49.95 dB이며, DNL과 INL은 각각 +0.57/-0.67, +1.73/-1.58이다.

• 디지털산업정보학회논문지
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• 제15권4호
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• pp.1-8
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• 2019

In this paper, we study the BESS of a standalone hybrid street light. The proposed BESS proposed a BESS with the function of efficiently charging irregularly generated power from two or more generators. AC generated by wind power is converted to DC using an AC / DC converter and then to a voltage that can charge the battery through the DC / DC converter. The lack of voltage and current, which is a disadvantage of the MPPT method used in solar power generation, is compensated by the DC value of wind power generation. The compensation method is to convert the DC generated from solar power into a voltage suitable for charging the battery through a DC / DC converter, and then connect the DC generated in wind power in parallel to compensate for the insufficient current to charge the battery in a short time. Allow this to begin. By securing the maximum charging time, the usage time of the stand-alone hybrid street light is huge. Experimental results show that the battery has a short charging time and can be efficiently applied to battery-dependent standalone hybrid street lights.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.