• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.233-239
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• 2009

A mixed CT/DT 2-1 cascaded ${\Sigma\Delta}M$ which includes a first stage CT ${\Sigma\Delta}M$ and a second stage mismatch insensitive two-channel time-interleaved DT ${\Sigma\Delta}M$ is proposed. With this approach, the advantages of both CT and DT ${\Sigma\Delta}Ms$ including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The two-channel time-interleaved ${\Sigma\Delta}M$ used in the second stage alleviates the speed constraints of the DT ${\Sigma\Delta}M$, whereas enables better matching between the analog and digital filter coefficients compared to CT ${\Sigma\Delta}Ms$.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.4
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• pp.64-69
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• 2009

Bit-interleaved coded modulation(BICM) applied to Alamouti's orthogonal space-time block code(OSIBC) has a rate loss problem In this paper, we expand orthogonal space-time block code(OSTBC) and apply bit-interleaved coded modulation (BICM) to expanded OSTBC(XOSIBC) to obtain a diversity gain without a rate loss. Binary phase shift keying(BPSK) design example is presented. Simulation results are also provided.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.3
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• pp.122-128
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• 2012

An interleaved boost converter has many advantages such as current ripple reduction, switching effective double, etc. Due to these advantages, the interleaved boost converter applies to the power factor correction circuit. However, there are almost no analysis results because the input voltage and current are time-varying system in the power factor correction application. Therefore, in this paper, the current ripples of the power factor correction circuit using single-phase boost dc-dc converter and 2-phase interleaved boost dc-dc converter are compared and analyzed in detail. In order to verify the validity, computer simulation and experimental are performed.

• Journal of Advanced Navigation Technology
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• v.27 no.5
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• pp.540-545
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• 2023

AESA radar is able to instantaneously and adaptively position and control the beam, and this enables to have interleaved mode in modern airborne AESA radar which can maximize situational awareness capability. Interleaved mode provides two or more modes simultaneously, such as Air to Air mode and Sea Surface mode by time sharing technique. In this interleaved mode, performance degradation is inevitable, compared with single mode operation, and effective resource allocation is the key component for the success of interleaved mode. In this paper, we identified performance evaluation items for each mode to analyze interleaved mode performance and proposed effective resource allocation methodology to achieve graceful performance degradation of each mode, focusing on detection range. We also proposed beam scheduling techniques for interleaved mode.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.59-63
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• 2015

This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in $0.13{\mu}m$ CMOS technology. The chip area was $760{\times}280{\mu}m^2$.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.1-8
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• 2004

In this paper, we investigate the properties and performance of space-time bit-interleaved coded modulation (STBICM) systems in fast Rayleigh fading channels. We first show that ST-BICM with QPSK signaling in fast fading channels possesses the uniform distance property, which makes performance analysis tractable. We also derive the probability distribution of the squared Euclidean distance between space-time symbols assuming uniform bit-interleaving. Based on the distribution, we show that the diversity order for each codeword pair becomes maximized as the frame length becomes sufficiently long. This maximum diversity order property implies that the bit-interleaver transforms an ST-BICM system over transmit diversity channels into an equivalent coded BPSK system over independent fading channels. We analyze the performance of ST-BICM in fast fading channels by deriving an FER upper bound. The derived bound turns out very accurate, requiring only the distance spectrum of the binary channel codes of ST-BICM. Numerical results demonstrate that the bound is tight enough to render an accurate estimate of performance of ST-BICM systems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.32-39
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• 2009

When adapting the transmitter to the channel state information(CSI), improved transmission is possible compared to the open loop system where no CSI is provided at the transmitter. However, since the perfect channel information is rarely available at the transmitter, the system design based on the partial CSI becomes an important factor. Especially, in mobile environments, the consideration for the outdated CSI should be applied for mitigating the performance degradation. In this paper, we propose a robust adaptive modulation and coding scheme for bit-interleaved coded orthogonal frequency division multiplexing over time-varying channels. With reasonable feedback overhead, the proposed scheme shows the enhanced performance by compensating for the outdated CSI due to Doppler spread. Simulation results confirm that the performance gain is achieved by applying an accurate BER estimation method.

• Journal of Power Electronics
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• v.5 no.3
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• pp.180-189
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• 2005

In this paper a DSP based control scheme for the interleaved boost converter is presented. The mathematical model for the interleaved boost converter operating in a continuous inductor current mode is developed. A state-space averaging technique is used for modeling the converter system. A fixed frequency sliding mode controller is designed to ensure current distribution between the two converter modules and to achieve the load voltage regulation simultaneously. Necessary and sufficient conditions, using variable structure theory, are derived for the sliding mode to exist. The range of sliding mode controller coefficients is also determined. The designed controller capability, load distribution among the individual boost cells and load voltage regulation against source and load disturbances, are demonstrated through PSIM simulation results. A real-time controller based on ADMC401 DSP is developed. Experimental results are provided to validate the proposed control scheme.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.107-112
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• 2020

We analyze the flow aggregate (FA) based network delay guarantee framework, with generalized minimal interleaved regulator (IR) initially suggested by IEEE 802.1 time sensitive network (TSN) task group (TG). The framework has multiple networks with minimal IRs attached at their output ports for suppressing the burst cascades, with FAs within a network for alleviating the scheduling complexity. We analyze the framework with various topology and parameter sets with the conclusion that the FA-based framework with low complexity can yield better performance than the integrated services (IntServ) system with high complexity, especially with large network size and large FA size.