• Journal of electromagnetic engineering and science
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• v.15 no.1
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• pp.53-58
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• 2015

For the testing of nonlinear power amplifiers, this paper suggests an approach to design optimized multisine signals that could be substituted for the original modulated signal. In the design of multisines, complex coefficients should be determined to mimic the target signal as much as possible, but very few methods have been adopted as general solutions to the coefficients. Furthermore, no solid method for the phase of coefficients has been proven to show the best resemblance to the original. Therefore, in order to determine the phase of multisine coefficients, a time-domain nonlinear optimization method is suggested. A frequency-domain-method based on the spectral response of the target signal is also suggested for the magnitude of the coefficients. For the verification, multisine signals are designed to emulate the LTE downlink signal of 10 MHz bandwidth and are used to test a nonlinear amplifier at 1.9 GHz. The suggested phase-optimized multisine had a lower normalized error by 0.163 dB when N = 100, and the measurement results showed that the suggested multisine achieved more accurate adjacent-channel leakage ratio (ACLR) estimation by as much as 12 dB compared to that of the conventional iterative method.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• Journal of Power System Engineering
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• v.6 no.3
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• pp.64-70
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• 2002

A fast decoupled algorithm for time domain simulation of power electronics circuits is presented. The circuits can be arbitrarily configured and can incorporate feedback amplifier circuits. This simulation algorithm is performed for the input series output parallel connected 2 switch forward converter. Steady state and large signal transient responses due to a step load change are simulated. The simulation results are verified through experiments.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.5 no.1
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• pp.60-69
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• 1980

The computerized analysis of complicated circuits requires large memory capacity and considerable length of time. In order to enhance the efficiency of memory capacity and the executing time, Sparse Matrix is applied to the solution of simultaneous equations required for the analysis of amplification circuit. The optimization Subroutine, FMFP is utilized for the decision of optimum element parameters of an equalizer amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1315-1322
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• 2012

Frequency domain reflectometry diagnoses faults on electric cables by measuring the cable impedance. Time domain impedance measurement technique using an oscilloscope instead of a network analyzer is widely used for electric power cables under harsh environment or powered condition. However, impedance measurement in the time domain shows inaccuracy as the frequency increases due to several parasitic impedances, which results in the poor resolution of fault points. This paper presents the accuracy enhancement technique using a module with an operational amplifier and an error calibration method in the time domain impedance measurements, which is confirmed by comparing the cable impedance measurement results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.