• Journal of Welding and Joining
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• v.32 no.3
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• pp.19-26
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• 2014

Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

• Korean Journal of Metals and Materials
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• v.48 no.6
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.553-554
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• 2010

• Journal of Surface Science and Engineering
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• v.55 no.6
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• pp.441-447
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• 2022

Silicon-based materials are one of the most promising anode active materials in lithium-ion battery. A carbon layer decorated on the surface of silicon particles efficiently suppresses the large volume expansion of silicon and improves electrical conductivity. Carbon coating through chemical vapor deposition (CVD) is one of the most effective strategies to synthesize carbon- coated silicon materials suitable for mass production. Herein, we synthesized carbon coated SiOx via pilot scale CVD reactor (P-SiO_x@C) and carbon coated SiO_x via industrial scale CVD reactor (I-SiO_x@C) to identify physical characteristic changes according to the CVD capacity. Reduced size silicon domains and local non-uniform carbon coating layer were detected in I-SiO_x@C due to non-uniform temperature distribution in the industrial scale CVD reactor with large capacity, resulting in increased surface area due to severe electrolyte consumption.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.18-18
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• 2008

3차원 패키징 System In Package (SIP)구조에서 Chip to Chip 단위 Interconnection 역할을 하는 Through Silicon Via(TSV)를 형성하기 위하여 Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용하였다. 이 Pulsating 플라즈마 공정 방법은 주기적인 펄스($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하며, 플라즈마 에칭특성에 영향을 주는 플라즈마즈마 발생 On/Off타임을 조절할 수 있다. 예를 들면, 플라즈마 발생 Off일 경우에는 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도 및 활성도를 급격하게 줄이는 효과를 얻을 수가 있는데, 이러한 효과는 식각 에칭시, 이온폭격의 손상을 급격하게 줄일 수 있으며, 실리콘 표면과 래디컬의 화학적 반응을 조절하여 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy- Fluoride)을 형성하는데 영향을 미친다. 그리고, TSV 형성에 있어서 큰 문제점으로 지적되고 있는 언더컷과 수평에칭 (Horizontal etching)을 개선하기 위한 방법으로, Black-Siphenomenon을 이번 실험에 적용하였다. 이 Black-Si phenomenon은 Bare Si샘플을 이용하여, 언더컷(Undercut) 및 수평 에칭 (Horizontal etching)이 최소화 되는 공정 조건을 간편하게 평가 할 수 있는 방법으로써, 에칭 조건 및 비율을 최적화하는 데 효율적이었다. 결과적으로, Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용한 에칭실험은 펄스 주파수($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하여, 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도와 활성화를 조절 하는데 효과적이었으며, Through Silicon Via (TSV)를 형성 하는데 있어서 Black-Si phenomenon 적용은 기존의 Continuous 플라즈마 식각 결과보다 향상된 에칭 조건 및 에칭 프로파일 결과를 얻는데 효과적이었다.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.69-73
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• 2010

Finite-element analyses were conducted to investigate the thermal stress in 3-dimensional stacked wafers package containing through-silicon-via (TSV), which is being widely used for 3-Dimensional integration. With finite element method (FEM), thermal stress was analyzed with the variation of TSV diameter, bonding diameter, pitch and TSV height. It was revealed that the maximum von Mises stresses occurred at the edge of top interface between Cu TSV and Si and the Si to Si bonding site. As TSV diameter increased, the von Mises stress at the edge of TSV increased. As bonding diameter increased, the von Mises stress at Si to Si bonding site increased. As pitch increased, the von Mises stress at Si to Si bonding site increased. The TSV height did not affect the von Mises stress. Therefore, it is expected that smaller Cu TSV diameter and pitch will ensure mechanical reliability because of the smaller chance of plastic deformation and crack initiation.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.739-740
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• 2011