• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1272-1278
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• 2009

The cancellation method of P/G(power/ground) plane resonances which are generated between the power plane and the ground plane in a 4-layer PCB(Printed Circuit Boards) with a via-hole for the improvement of the RE(Radiated Emission) characteristic is presented. The validity of the proposed method was confirmed from simulation and measurement of performances of signal transmission characteristic, intensities of edge-radiation and radiated emission of PCB with a via-hole.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1112-1117
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• 2006

The properties of LTCC green tape with addition of binder were investigated in order to understand an effects of binder on multilayer processing. A green sheet form was fabricated through tape casting method with the MLS-22 powder. The lamination density increased with increasing amount of binder and lamination pressure. With increasing amount of binder, the elongation of ceramic sheets increased but the tensile stress and air-permeability decreased. The addition of excessive binder is caused defects in the green sheet during via hole punching. The optimum condition of the via hole without defects was observed from amount of the binder 10 wt%.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.3
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• pp.73-79
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• 2008

Atomization speed of diesel fuel injected from 8-hole nozzle is faster than that of 7-hole nozzle because the hole diameter of 8-hole nozzle is smaller than that of 7-hole nozzle. But both insufficient distance between the fuel sprays and short penetration of injected sprays through 8-hole nozzle hole cause many harmful effects on combustion. In this study, we installed the 8-hole injectors to diesel 2.0 liter class engine, and optimized in-cylinder swirl and penetration via selecting and matching proper cylinder head and combustion bowl. Through this process, we found out the performance and emission potential of 8-hole nozzle installed engine are better than those of 7-hole nozzle installed one.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.45-52
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• 2005

This paper presents the characterization of through hole vias on printed circuit board (PCB) through the time domain and frequency domain measurements. The time domain measurement was performed on a single via using the TDR, and the model parameters were extracted by the fitting simulation using HSPICE. The frequency domain measurement was also performed by using 2 port VNA, and the model parameters were extracted by fitting simulation with ADS. Using the ABCD matrices, the do-embedding equations were derived probing in the same plane in the VNA measurement. Based on the single via characterization, the differential via characterization was also performed by using TDR measurements. The time domain measurements were performed by using the odd mode and even mode sources in TDR module, and the Parameter values were extracted by fitting with HSPICE. Comparing measurements with simulations, the maximum calculated differences were $14\%$ for single vias and $17\%$ for differential vias.

• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.55-58
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• 2018

Low-cost and large-scale fabrication method of nanohole array, which comprises nanoscale voids separated by a few tens to a few hundreds of nanometers, has opened up new possibilities in biomolecular sensing as well as novel frontier optical devices. One of the key aspects of the nanohole array research is how to control the hole size following each specific needs of the hole structure. Here, we report the extensive study on the fine control of the hole size within the range of 500-2500 nm via surface-catalyzed chemical deposition. The initial hole structures were prepared via conventional photo-lithography, and the hole size was decreased to a designed value through the surface-catalyzed chemical reduction of the gold ion on the predefined hole surfaces, by simple dipping of the hole array device into the aqueous solution of gold chloride and hydroxylamine. The final hole size was controlled by adjusting reaction time, and the optimal experimental condition was obtained by doing a series of characterization experiments. The characterization of size-controlled hole array was systematically examined on the image results of optical microscopy, field emission scanning electron microscopy(FESEM), atomic-force microscopy(AFM), and total internal reflection microscopy.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.5-5
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• 2004

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.94-98
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• 2023

In the case of high-speed data transmission on high multilayer boards, signal coherence is a problem, especially due to the via hole, and a solution to improve return loss or insertion loss by applying a back drill to the via hole is being proposed. In this paper, Near-Field Electromagnetic measurements were made on a high multilayer board to determine how the presence or absence of back drill affects signal consistency. For this purpose, we used a signal generator, spectrum analyzer, and EMC scanner on a test board to determine if it is possible to distinguish between areas with and without back drill in the via holes of the stubs on the board. Also, we analyzed the measured value of S11, S21 and EMC etc. for how much it improves the signal attenuation of the stub with back drill. Through this, we knew that less electromagnetic waves are generated the stub via with back drill. At future research, we will analyze how much it improves the signal loss and electromagnetic waves due to the depth of back drill.