• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권1호
• /
• pp.141-146
• /
• 2017

In this letter, we propose the use of tunneling field effect transistors (TFET) as a biosensor that detects bio-molecules on the gate oxide. In TFET sensors, the charges of target molecules accumulated at the surface of the gate oxide bend the energy band of p-i-n structure and thus tunneling current varies with the band bending. Sensing parameters of TFET sensors such as threshold voltage ($V_t$) shift and on-current ($I_D$) change are extracted as a function of the charge variation. As a result, it is found that the performances of TFET sensors can surpass those of conventional FET (cFET) based sensors in terms of sensitivity. Furthermore, it is verified that the simultaneous sensing of two different target molecules in a TFET sensor can be performed by using the ambipolar behavior of TFET sensors. Consequently, it is revealed that two different molecules can be sensed simultaneously in a read-out circuit since the multi-sensing is carried out at equivalent current level by the ambipolar behavior.

• 한국전기전자재료학회논문지
• /
• 제25권1호
• /
• pp.24-28
• /
• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.470-470
• /
• 2012

Organic thin film transistors (OTFTs) backplane constitute the active elements in new generations of plastic electronic devices for flexible display. The overall OTFTs performance is largely depended on the properties and quality of each layers of device material. In solution based process of organic semiconductors (OSCs), the interface state is most impediments to preferable performance. Generally, a threshold voltage (Vth) shift is usually exhibited when organic gate insulators (OGIs) are exposed in an ambient air condition. This phenomenon was caused by the absorbed polar components (i.e. oxygen and moisture) on the interface between OGIs and Soluble OSCs during the jetting process. For eliminating the polar component at the interface of OGI, the role of high vacuum seasoning on an OGI for all solution processable OTFTs were studied. Poly 4-vinly phenols (PVPs) were the material chosen as the organic gate dielectric, with a weakness in ambient air. The high vacuum seasoning of PVP's surface showed improved performance from non-seasoning TFT; a $V_{th}$, a ${\mu}_{fe}$ and a interface charge trap density from -8V, $0.018cm^2V^{-1}s^{-1}$, $1.12{\times}10^{-12}(cm^2eV)^{-1}$ to -4.02 V, $0.021cm^2V^{-1}s^{-1}$, $6.62{\times}10^{-11}(cm^2eV)^{-1}$. These results of OTFT device show that polar components were well eliminated by the high vacuum seasoning processes.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.523-523
• /
• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.118-118
• /
• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• 한국정보통신학회논문지
• /
• 제21권9호
• /
• pp.1627-1634
• /
• 2017

비정질 InGaZnO 박막 두께가 다른 무접합 트랜지스터를 제작하고 두께에 따른 양과 음의 게이트 스트레스 전압 및 빛을 비춘 상태에서 소자 불안정성을 분석하였다. 채널 박막 두께가 얇을수록 게이트 스트레스 및 빛이 인가된 상태에서 문턱전압 및 드레인 전류 변화가 큰 것을 알 수 있었다. 그 원인을 stretched-exponential 모델과 소자 시뮬레이션을 수행하여 설명하였다. 박막이 얇을수록 캐리어 트랩핑 시간이 짧기 때문에 전자나 홀이 빨리 활성화되는 것과 채널 박막의 뒷부분에서 채널의 수직 전계가 증가하여 전자나 홀을 많이 축적할 수 있는 것으로 설명하였다. IGZO 무접합 트랜지스터 제작에서 채널 박막의 두께를 결정할 때 채널 박막 두께가 얇을수록 소자 불안정성이 큰 것을 고려해야 됨을 알 수 있다.

• 대한금속재료학회지
• /
• 제48권3호
• /
• pp.256-261
• /
• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• 한국재료학회지
• /
• 제33권11호
• /
• pp.491-496
• /
• 2023

As the demand for p-type semiconductors increases, much effort is being put into developing new p-type materials. This demand has led to the development of novel new p-type semiconductors that go beyond existing p-type semiconductors. Copper iodide (CuI) has recently received much attention due to its wide band gap, excellent optical and electrical properties, and low temperature synthesis. However, there are limits to its use as a semiconductor material for thin film transistor devices due to the uncontrolled generation of copper vacancies and excessive hole doping. In this work, p-type CuI semiconductors were fabricated using the chemical vapor deposition (CVD) process for thin-film transistor (TFT) applications. The vacuum process has advantages over conventional solution processes, including conformal coating, large area uniformity, easy thickness control and so on. CuI thin films were fabricated at various deposition temperatures from 150 to 250 ℃ The surface roughness root mean square (RMS) value, which is related to carrier transport, decreases with increasing deposition temperature. Hall effect measurements showed that all fabricated CuI films had p-type behavior and that the Hall mobility decreased with increasing deposition temperature. The CuI TFTs showed no clear on/off because of the high concentration of carriers. By adopting a Zn capping layer, carrier concentrations decreased, leading to clear on and off behavior. Finally, stability tests of the PBS and NBS showed a threshold voltage shift within ±1 V.

• ETRI Journal
• /
• 제38권4호
• /
• pp.675-684
• /
• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• 대한전자공학회논문지SD
• /
• 제45권5호
• /
• pp.19-25
• /
• 2008

본 연구에서는 유기반도체인 펜타센과 소스-드레인 금속전극사이에 $C_{60}$을 홀주입층으로 적용한 유기박막트랜지스터를 제작하여 $C_{60}$을 삽입하지 않은 소자와의 전기적특성을 비교하였다. $C_{60}/Au$ 이중전극을 사용한 소자의 경우 Au단일전극을 사용한 소자와 비교하였을 때 전하이동도는 0.298 $cm^2/V{\cdot}s$에서 0.452 $cm^2/V{\cdot}s$ 문턱전압의 경우 -13.3V에서 -10.8V로 향상되었으며, contact resistance를 추출하여 비교하였을 경우 감소함을 확인할 수 있었다. 이러한 성능의 향상은 $C_{60}$을 Au와 pentacene 사이에 삽입하였을 경우 Au-pentacene 간의 원하지 않는 화학적 반응을 막아줌으로써 홀 주입장벽를 감소시켜 홀 주입이 향상되었기 때문이다. 또한 Al을 전극으로 적용한 OTFT도 제작하였다. 기존에 Al은 OTFT에 단일전극으로 사용하였을 경우 둘간의 높은 홀 주입장벽으로 인해 채널이 거의 형성되지 않았으나, $C_{60}/Al$ 이중전극을 사용한 소자의 경우 전하이동도와 전류점멸비은 0.165 $cm^2/V{\cdot}s$, $1.4{\times}10^4$ 으로써 Al를 단일전극으로 사용하는 소자의 전기적 특성에 비해 크게 향상되어진 소자를 제작할 수 있었다. 이는 $C_{60}$과 Al이 접합시에 interface dipole의 형성으로 Al의 vacuum energy level이 변화로 인한 Al의 work function이 증가되어 pentacene과 Al간의 hole injection barrier가 감소되었기 때문이다.