• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.