• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.151-158
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• 2002

Fabricated were ultra-shallow $p^+-n$ junctions on n-type Si(100) substrates using decaborane $(B_{10}H_{14})$ ion implantation. Decaborane ions were implanted at the acceleration voltages of 5 kV to 10 kV and at the dosages of $1\times10^{12}\textrm{cm}^2$.The implanted specimens were annealed at $800^{\circ}C$, $900^{\circ}C$ and $1000^{\circ}C$ for 10 s in $N_2$ atmosphere through a rapid thermal process. From the measurement of the implantation-induced damages through $2MeV^4 He^{2+}$ channeling spectra, the implanted specimen at the acceleration voltage of 15 kV showed higher backscattering yield than those of the bare n-type Si wafer and the implanted specimens at 5 kV and 10 kV. From the channeling spectra, the calculated thicknesses of amorphous layers induced by the ioin implantation at the acceleration voltages of 5 kV, 10 kV and 15 kV were 1.9 nm, 2.5 nm and 4.3 nm, respectively. After annealing at $800^{\circ}C$ for 10 s in $N_2$ atmosphere, most implantation-induced damages of the specimens implanted at the acceleration voltage of 10 kV were recovered and they exhibited the same channeling yield as the bare Si wafer. In this case, the calculated thickness of the amorphous layer was 0.98 nm. Hall measurements and sheet resistance measurements showed that the dopant activation increased with implantation energy, ion dosage and annealing temperature. From the current-voltage measurement, it is observed that leakage current density is decreased with the increase of annealing temperature and implantation energy.

• Journal of the Korean institute of surface engineering
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• v.52 no.6
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• pp.283-288
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• 2019

MCrAlY overaly coatings are used as oxidation barrier coatings to prevent degradation of the underlying substrate in high temperature and oxidizing environment of the hot section of gas turbines. Therefore, oxidation resistance in high temperature is important property of MCrAlY coatings. Also, coefficients of thermal expansion (CTE) of MCrAlY have middle value of that of Ni-based superalloys and oxides, which have the effect of preventing the delamination of the surface oxides. Cyclic oxidation test is one of the most useful methods for evaluating the high temperature durability of coatings used in gas turbines. In this study, NiCoCrAlY overlay coatings were formed on Inconel 792(IN 792) substrates by vacuum plasma spraying process. Vacuum plasma sprayed NiCoCrAlY coatings and IN 792 susbstrates were exposed to 1000℃ one-hour cyclic oxidation environment. NiCoCrAlY coatings showed lower weight gain in short-term oxidation. In long-term oxidation, IN 792 substrates showed higher weight loss due to delamination of surface oxide but NiCoCrAlY coatings showed lower weight loss. X-ray diffraction (XRD) analysis showed α-Al2O3 and NiCr₂O₄ was formed during the cyclic oxidation test. Through cross-section observation using scanning electron microscopy (SEM) and electron back scatter diffraction (EBSD) analysis, thermally grown oxide (TGO) layer composed of α-Al₂O₃ and NiCr₂O₄ was formed and the thickness of TGO increased during 1000℃ cyclic oxidation test. β phase in upper side of NiCoCrAlY coating was depleted due to oxidation of Al and outer beta depletion zone thickness also increased as the cyclic oxidation time increased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.25-32
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• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Polymer(Korea)
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• v.33 no.1
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• pp.79-83
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• 2009

Thin electric insulation layers were coated on aluminum plates and aluminum condenser cases by plasma polymerization of HMDSO+$O_2$. Electric resistances of the films were higher than 1.0 M$\Omega$ if they are thicker than 0.5 ${\mu}m$ independently of the type of films but their surface morphologies and adhesion strengths were dependent on the process conditions. Deposition rate and adhesion strength of the films were dependent on $O_2$/HMDSO flow ratio and discharge power. The best result was obtained at $O_2$/HMDSO flow ratio of 4 and discharge power of 60 W. Adhesion strength could also be highly improved if aluminum was pre-treated in boiling water for 30 min through the formation of Al-O-Si bonding between the film and the aluminum surface. The coated films showed excellent chemical and thermal resistances.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.99-105
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• 2022

As the chip size gets smaller, the width of the electrode line is also fine, and the density of interconnections is increasing. As a result, RC delay is becoming a problem due to the difference in resistance between the capacitor layer and the electrical conductivity layer. To solve this problem, the development of electrodes with high electrical conductivity and dielectric materials with low dielectric constant is required. In this study, we developed low dielectric ink by mixing commercial PSR which protect PCB's circuits from external factors and PI with excellent thermal property and low-k characteristics. As a result, the ink mixture of PSR and PI 10:3 showed the best results, with a dielectric constant of about 2.6 and 2.37 at 20 GHz and 28 GHz, respectively, and dielectric dissipation was measured at about 0.022 and 0.016. In order to verify the applicability of future applications, various line-width transmission lines produced on Teflon were evaluated, and as a result, the loss of transmission lines using low dielectric ink mixed with PI was 0.12 dB less on average in S21 than when only PSR was used.

• Korean Journal of Materials Research
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• v.2 no.6
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• pp.408-416
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• 1992

Stable TiS$i_2$was formed by RTA on single-Si and on poly-Si. Subsequently, an Al-1% Si layer with 600-nm thick was deposited on top of the TiS$i_2$, Finally, the specimens were annealed for 30min at 400-60$0^{\circ}C$in $N_2$ambient. The thermal stability of Al-1% Si/TiS$i_2$bilayer and interfacial reaction were investigated by measuring sheet resistance, Auger electron spectroscopy (AES), and scanning electron microscopy (SEM). The composition and phase of precipitates formed by the reaction of Al-1% Si with Ti-silicide were studied by energy dispersive spectroscopy (EDS), X-ray diffraction (XRD). In the case of single-Si substrate the reaction of Al-1% Si layer with TiS$i_2$layer resulted in precipitates, consuming all TiS$i_2$layer at 55$0^{\circ}C$. On the other hand, the disappearance of TiS$i_2$on poly-Si occurred at 50$0^{\circ}C$ and more precipitates were formed by the reaction of Al-1% Si/TiS$i_2$on potty-Si substrate than those of the reaction on single-Si substrate. This phenomenon resulted from the fact that Ti-silicide formed on poly-Si was more unstable than on single-Si by the effect of grain boundary. By EDS analysis the precipitates were found tobe composed of Ti, Al, and Si. X-ray diffraction showed the phase of precipitates to be theT$i_7$A$l_5$S$i_12$ternary compound.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.528-537
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• 2008

60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm $SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-$SiO_2$/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from $400^{\circ}C$ which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from $300^{\circ}C$. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at $300^{\circ}C$.

• Journal of Korean Tunnelling and Underground Space Association
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• v.15 no.3
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• pp.289-300
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• 2013

This study numerically considered the characteristic of smoke movement and the effect of hot smoke gas on tunnel wall surface temperature during road tunnel fire under boundary condition of fire growth curve that is applied to fire analysis in road tunnels. The maximum heat release rate were 20 MW and 100 MW and tunnel air velocities were 2.5 m/s and velocity induced by thermal buoyancy respectively, also the cooling effect of tunnel wall was considered. As results, when tunnel air velocity was constant at 2.5 m/s during tunnel fire, due to the cooling effect of tunnel wall, the smoke layer was rapidly descent after some distance and it flowed the same patterns at the downstream. When heat release rate was 100 MW (and jet fan was not installed), the maximum temperature of tunnel wall surface has risen up to $615^{\circ}C$. The heat transfer coefficient of tunnel wall surface was varied from 13 to $23W/m^2^{\circ}C$ approximately.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Solar Energy
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• v.17 no.4
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• pp.3-11
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• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.