• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1633-1640
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• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1283-1287
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• 2004

The design rules are being more strict with requirement of operation speed and development of IC industry. For this reason, required minimum line-width has been narrowed under sub-micron region. As the length of minimum line-width is narrowed, local and global planarization are being prominent. CMP(Chemical-Mechanical Polishing), one of the planarizarion technology, is a process which polishes with the ascent of chemical reaction and relative velocity between pad and wafer without surface defects. CMP is performed with a complex interaction among many factors, how CMP has an interaction with such factors is not evident. Accordingly, the studies on this are still carrying out. Therefore, an examination of the CMP phenomena and an accurate understanding of compositive factors are urgently needed. In this paper, we will consider of the relations between the effects of temperature which influences many factors having an effect on polishing results and the characteristics of CMP in order to understand and estimate the influence of temperature. Then, through the interaction of shown temperature and polishing result, we could expect to boost fundamental understanding on complex CMP phenomena.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.37-45
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• 2008

In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at $250^{\circ}C\;and\;280^{\circ}C$, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at $125^{\circ}C$ up to 2000 hours. However, bump contact resistances slightly increased at $150^{\circ}C$ due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.10
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• pp.817-822
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• 2017

The braking system is one of the most important components in vehicles and machines. It must exert a reliable braking force when they are brought to a halt. Generally, frictional heat is generated by converting kinetic energy into heat energy through friction. As the kinetic energy is converted into heat energy, high temperature heat is generated which affects the mechanical behavior of the braking system. Frictional heat affects the thermal expansion and friction coefficient of the brake system. If the temperature is not controlled, the brake performance will be decreased. Therefore, it is important to predict and control the heat generation of the brake. Various numerical analysis studies have been carried out to predict the frictional heat, but they assumed the existence of boundary conditions in the numerical analysis to simulate the frictional heat, because the simulation of frictional heat is difficult and time consuming. The results were based on the assumption that the frictional heat is different from the actual temperature distribution in a rotating brake system. Therefore, the reliability of the cooling effect or thermal stress using the results of these studies is insufficient. In order to overcome these limitations and establish a simulation procedure to predict the frictional heat, this study directly simulates the frictional heat generation by using a thermal-structure coupling element. In this study, we analyzed the thermo-mechanical behavior of a brake model, in order to investigate the thermal characteristics of brake systems by using the Finite Element method (FEM). This study suggests the necessity to directly simulate the frictional heating and it is hoped that it can provide the necessary information for simulations.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.33-38
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• 2007

We studied a bonding at low temperature using polymer bump and Non-Conductive Adhesive (NCA), and studied the reliability of the polymer bump/Al pad joints. The polymer bumps were formed on oxidized Si substrates by photolithography process, and the thin film metals were formed on the polymer bumps using DC magnetron sputtering. The substrate used was AL metallized glass. The polymer bump and Al metallized glass substrates were joined together at $80^{\circ}C$ under various pressure. Two NCAs were applied during joining. Thermal cycling test ($0^{\circ}C-55^{\circ}C$, cycle/30 min) was carried out up to 2000 cycles to evaluate the reliability of the joints. The bondability was evaluated by measuring the contact resistance of the joints through the four point probe method, and the joints were observed by Scanning Electron Microscope (SEM). The contact resistance of the joints was $70-90m{\Omega}$ before the reliability test. The joints of the polymer bump/Al pad were damaged by NCA filler particles under pressure above 200 MPa. After reliability test, some joints were electrically failed since thinner metal layers deposited at the edge of bumps were disconnected.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.45-54
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• 2020

Recently, market demands of miniaturization, high interconnection density, and fine pitch of PCBs continuously keep increasing. Therefore, SLP (substrate like PCB) technology using a modified semi additive process (MSAP) has attracted great attention. In particular, SLP technology is essential for the development of high-capacity batteries and 5G technology for smartphones. In this study, the reliability of the microvia of hybrid SLP, which is made of conventional HDI (high density interconnect) and MSAP technologies, was investigated by experimental and numerical analysis. Through thermal cycling reliability test using IST (interconnect stress test) and finite element numerical analysis, the effects of various parameters such as prepreg properties, thickness, number of layers, microvia size, and misalignment on microvia reliability were investigated for optimal design of SLP. As thermal expansion coefficient (CTE) of prepreg decreased, the reliability of microvia increased. The thinner the prepreg thickness, the higher the reliability. Increasing the size of the microvia hole and the pad will alleviate stress and improve reliability. On the other hand, as the number of prepreg layers increased, the reliability of microvia decreased. Also, the larger the misalignment, the lower the reliability. In particular, among these parameters, CTE of prepreg material has the greatest impact on the microvia reliability. The results of numerical stress analysis were in good agreement with the experimental results. As the stress of the microvia decreased, the reliability of the microvia increased. These experimental and numerical results will provide a useful guideline for design and fabrication of SLP substrate.

• International Journal of Oral Biology
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• v.39 no.1
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• pp.49-56
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• 2014

We investigated the role of central P2X receptors in inflammatory pain transmission in the orofacial area in rats. Experiments were carried out using male Sprague-Dawley rats weighing 230-280g. Complete Freund's adjuvant (CFA, $40{\mu}L$) was applied subcutaneously to the vibrissa pad to produce inflammatory pain. The intracisternal administration of iso-PPADS tetrasodium salt, a non-selective P2X receptor antagonist, A317491 sodium salt hydrate, a $P2X_{2/3}$ receptor antagonist, 5-BDBD, a $P2X_4$ receptor antagonist, or A438079 hydrochloride, a $P2X_7$ receptor antagonist, was performed 5 days after CFA injection. Subcutaneous injections of CFA produced increases in thermal hypersensitivity. Intracisternal injections of iso-PPADS ($25{\mu}g$) or A438079 (25 or $50{\mu}g$) produced significant anti-hyperalgesic effects against thermal stimuli compared to the vehicle group. A317491 or 5-BDBD did not affect the head withdrawal latency times in rats showing an inflammatory response. Subcutaneous injections of CFA resulted in the up-regulation of OX-42, a microglia marker, and GFAP, an astrocyte marker, in the medullary dorsal horn. The intracisternal administration of A438079 reduced the numbers of activated microglia and astrocytes in the medullary dorsal horn. These results suggest that a blockade of the central $P2X_7$ receptor produces antinociceptive effects, mediated by inhibition of glial cell function in the medullary dorsal horn. These data also indicate that central $P2X_7$ receptors are potential targets for future therapeutic approaches to inflammatory pain in the orofacial area.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.47-53
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• 2012

Bonding strength of Sn-3.0Ag-0.5Cu solder joint due to degradation characteristic of OSP surface finish was investigated, compared with SnPb finish. The thickness variation and degradation mechanism of organic solderability preservative(OSP) coating were also analyzed with the number of reflow process. To analyze the degradation degree of solder joint strength, FR-4 PCB coated with OSP and SnPb were experienced preheat treatment as a function of reflow number from 1st to 6th pass, respectively. After 2012 chip resistors were soldered with Sn-3.0Ag-0.5Cu on the pre-heated PCB, the shear strength of solder joints was measured. The thickness of OSP increased with increase of the number of reflow pass by thermal degradation during the reflow process. It was also observed that the preservation effect of OSP decreased due to OSP degradation which led Cu pad oxidation. The mean shear strength of solder joints formed on the Cu pads finished with OSP and SnPb were 58.1 N and 62.2 N, respectively, through the pre-heating of 6 times. Although OSP was degraded with reflow process, the feasibility of its application was proven.