• 대한전기학회논문지:시스템및제어부문D
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• 제52권12호
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• pp.671-678
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• 2003

This paper proposes an expert system to generate automatically the test table of test system which can highly enhance the quality and productivity of product by inspecting quickly and accurately the defect device on the electronic circuit board tested. The expert system identifies accurately the tested components and the circuit patterns by tracing automatically the connectivity of circuit from electronic circuit database. And it generates automatically the test table to detect accurately the missing components, the misplaced components, and the wrong components for analog components such as resistance, coil, condenser, diode, and transistor, based on the experience knowledge of veteran expert. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. And, the validity of the builded expert system is proved by simulating for a typical electronic board model.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2196-2198
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• 2001

Because the circuit board has the structure connected by circuit patterns, the work to test whether the analog devices or circuits such as resisters, capacitors, inductors, diodes, etc. on the tested board is goof or not is very difficult. This paper proposes the test method of identifing the faulted devices or faulted circuit on the circuit board using guarding circuit. The guarding method is the techniqus measuring accurately the value of the devices by separating the electronic devices to be tested from around it. Finally, the availability and accuracy of the proposed test method is verified by applying the technique to a test electronic circuit.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권8호
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• pp.475-481
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• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.705-706
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• 2006

Generally Short Circuit Test of transformers are tested according to IEEE std C57.12.00-2000, IEC 60076-5(2000-07), ES148(1998.6.26) or KS C4309(2003). But ES148(1998.6.26) is same as IEEE std C57. 12.00-2000 and KS C4309(2003) is revising coincidence with IEC 60076-5(2000-07). On this study condition of the transformers before short circuit test, calculation method for test current peak value, tolerance on the asymmetrical peak and r.m.s value, short circuit testing procedure, number of short circuit test, duration short circuit test, and detection of faults and evaluation of short circuit test result will be compared with ANSI and IEC.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 A
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• pp.357-359
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• 2003

This paper is for the transient analysis of instant short-circuit test equipment according to the test of tripping limits and characteristics under IEC 60947-2. The in-rush current is harmful to almost equipments and the exact testing is not made because of it. LGIS has a instant short-circuit test equipment, but it is not suitable for carrying out instant short-circuit test on ELB(Earth Leakage Circuit breaker) by reason of that. Now, I am going to show a solution for that problem. After applying this method, manufacturer is going to acquire the exact testing result according to the IEC standard. Moreover, Testing laboratory will be trusted by clients.

• 대한전자공학회논문지
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• 제24권5호
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• pp.896-904
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• 1987

In this paper, a design method for sequential circuit which is easy to have Built-in Self Test is kproposed using the functional advantages of multifunctional BILBO and LSSD. To achieve the hardware reduction, it is designed that a multifunctional BILBO has double operational functions of NLFSR and LFSR, when neccessary, and that test signal could be used as an input-output signal in the same line. By applying the proposed multifunctional BILBO to the sequential PLA, the test patterns and the additional circuit could be reduced in test operation and the propagation delay is vanished in normal operation, as we expected. Above them, the partitioned method for large scale sequential circuit is also suggested and it is observed that test patterns and additional circuit in them reduced by this method.

• 전력전자학회논문지
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• 제28권1호
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• pp.76-81
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• 2023

A new test circuit for an MMC-based valve HVDC power converter is proposed. The proposed scheme satisfies the required clauses from IEC-62501. The valve test current contains second harmonic component and DC offset as well as a fundamental component that is quite similar to the real operating arm current of MMC based HVDC power system. The structure of the proposed test circuit is simple compared to conventional test circuits. Furthermore, the power supply voltage rating of the proposed test circuit is reduced dramatically around 20% of the conventional scheme with the same current rating. The validity of the proposed test circuit is verified through simulation and experimental results.

• 한국통신학회논문지
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• 제19권6호
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• pp.1038-1045
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• 1994

본 논문에서는 CAM에서 발생하는 모든 PSF(Pattern Sensitive Fault)를 검사하기 위한 알고리즘과 테스트회로를 설계하였다. 즉, 짧은 시간에 최소의 부가회로를 이용하여 외부의 장비에 의존하지 않고 테스트하는 내장 테스트회로를 설계하였다. 부가적으로 첨가된 회로로는 병렬비교기와 오류검출기가 있고, 병렬테스팅을 위해서 수정된 디코더를 사용하였다. 또한, 효과적인 테스트패턴을 구하기 위해 Eulerian path의 구성방법에 대해서도 연구를 수행하였다. 결과적으로, 본 논문에서 사용한 알고리즘을 사용하면 워드수에 관계없이 324+2b(b:비트수) 만큼의 동작으로 CAM의 모든 내용을 테스트할 수 있다. 전체 회로중에서 테스트회로가 차지하는 면적은 약 7.5%정도가 된다.

• 대한전기학회논문지:전력기술부문A
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• 제54권6호
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• pp.284-292
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• 2005

Because all of the short-circuit testing laboratories have the limitation of test facilities, the synthetic making test methods have been used to estimate the short-circuit making performance of the ultra high-voltage circuit breaker as the alternative to direct test methods. So, KERI(Korea Eelctrotechnology Research institute) has completed the construction of the synthetic making test facilities using the low capacity step-up transformer method which fulfill the requirements specified in newly revised IEC 62271-100 Edition 1.1(2003) and have the testing capability up to 550kV, 63kA full-pole circuit breaker. The test facilities using the low capacity step-up transformer method presented in this paper are made up of the unit equipments such as HCS(High-speed Closing Switch), ITMC(Initial Transient Making Current) circuit and UP TR(low capacity step-up transformer) and have the operating range of 17.6$^{\circ}$ $\~$ 145.1$^{\circ}$ for testing the circuit breaker rated on up to 50kA and 43.1$^{\circ}$ $\~$ 119.6$^{\circ}$ for more than 50kA.