• 한국막학회:학술대회논문집
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• 한국막학회 2002년도 제15회 심포지움
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• pp.23-46
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• 2002

The cryogenic, pressure swing adsorption and membrane methods have been used to separate air into nitrogen and oxygen. The air separation membrane is made of the polymers, of which manufacturing process is complicate and it causes a little high production cost. Polymer membrane has temperature limit in usage and low durability even at moderate temperature. Therefore, inorganic membranes have been studied for years. As formation of unit alumino-silicate membrane, unit cells of membrane were made with a few coating methods. In this study the dipping of substrate into sols, application of vacuum to the opposite side of substrate with coating and rotating of the substrate in the sols were found as good coating memthods to make a uniform coating and to control the thickness of membrane. The membrane coats were examined by SEM and XRD. The sample ESZl-1 was compared with those of samples that prepared by another method. The present developed coating methods could be applied to the various types of zeolite membrane formation, that is A- X-, Y- ZSM- and MCM-types of membranes. Also these membrane forming methods could be applied to formation of catalyst absorbed zeolite membrane, of which zeolite absorb the catalytic metals. The product obtained from these coating methods could be applied to the industrial gas and liquid phase catalytic reaction and separation processes.

• Advances in nano research
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• 제10권1호
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• pp.91-99
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• 2021

Silicene is an emerging two-dimensional (2D) semiconductor material which has been envisaged to be compatible with conventional silicon technology. This paper presents a theoretical study of uniformly doped silicene with aluminium (AlSi3) Field-Effect Transistor (FET) along with the benchmark of device performance metrics with other 2D materials. The simulations are carried out by employing nearest neighbour tight-binding approach and top-of-the-barrier ballistic nanotransistor model. Further investigations on the effects of the operating temperature and oxide thickness to the device performance metrics of AlSi3 FET are also discussed. The simulation results demonstrate that the proposed AlSi3 FET can achieve on-to-off current ratio up to the order of seven and subthreshold swing of 67.6 mV/dec within the ballistic performance limit at room temperature. The simulation results of AlSi3 FET are benchmarked with FETs based on other competitive 2D materials such as silicene, graphene, phosphorene and molybdenum disulphide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• 한국재료학회지
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• 제26권12호
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• pp.676-680
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• 2016

We have investigated the properties of thin film transistors(TFT) fabricated using zinc tin oxide(ZTO) thin films deposited via on-axis sputtering and FTS methods. ZTO thin films deposited by FTS showed lower root-mean-square(RMS) roughness and more uniformity than those deposited via on-axis sputtering. We observed enhanced electrical properties of ZTO TFT deposited via FTS. The ZTO films were deposited at room temperature via on-axis sputtering and FTS. The as-deposited ZTO films were annealed at $400^{\circ}C$. The TFT using the ZTO films deposited via FTS process exhibited a high mobility of $12.91cm^2/V.s$, a low swing of 0.80 V/decade, $V_{th}$ of 5.78 V, and a high $I_{on/off}$ ratio of $2.52{\times}10^6$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1249-1252
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• 2007

We have fabricated 3.5” transparent AM-OLED panel driven by PEALD grown ZnO TFT. The performance of ZnO thin film transistor was improved by adapting top gate structure, protection layer for ZnO from photolithography process, optimizing temperature and plasma power of ZnO growth process. The ZnO-TFT has a mobility of $8.9cm^2/V.s$, a subthreshold swing of 0.95V, and an on/off ratio of $10^7$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.439-442
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• 2006

We evaluated a-Si:H TFTs fabricated on polyimide substrate (PI) at the highest temperature of $160^{\circ}C$ with uniaxial and tensile strain to imitate flexible display. With tensile strain, the threshold voltage of a-Si:H TFTs have positive shift due to extra dangling bond formation in a-Si:H layer. However, no significant degradation of the subthreshold swing and effective mobility with tensile strain of a-Si:H TFTs indicates the similar level of band tail state. The metal wire with the width of $10\;{\mu}m$ for connection on flexible substrate can sustain with curvature radius 2.5 cm.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.356-356
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• 2010

In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.309-309
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• 2000

The main objective of this study is to understand the regeneration step of the PTSA(Pressure and thermal swing adsorption) process below the atmospheric pressure by rigorous dynamic simulation. This target process is to recover toluene using activated carbon as an adsorbent. To do this, the dynamic simulations for the regeneration step are performed at 360, 490, 590mmHg and at high temperature after the simulation of the adsorption step at latm and 298K. A mathematical model was developed to simulate the column dynamics of the adsorption systems. This model is based on non-equilibrium, non-isothermal and non-adiabatic conditions, and axial dispersion and heat conduction are also considered. Heat transfer resistances are considered in gas-solid, gas-column wall and column wall-outside air. The LDF(Linear Driving Force) approximation model describes the mass transfer rate between the gas and solid phase. This study shows that the recovery of toluene by PTSA is more preferable than that by general TSA.

• Journal of Information Display
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• 제6권4호
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.