• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.649-657
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• 2014

In this study, the effects of the frequency-dependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is composed of 32-nm CMOS inverter drivers and receivers connected through TSVs. The frequency-domain model of TSVs is extracted in S-parameter from a 3D electromagnetic (EM) method, where the dimensional variation effect of TSVs can be accurately considered for a comprehensive parameter sweep simulation. A parametric analysis shows that the propagation delay increases with the diameter and height of the TSVs but decreases with the pitch and liner thickness. We also investigate the crosstalk effect between TSVs by testing different signaling conditions. From the simulations, the worst signal integrity is observed when the signal experiences a simultaneously coupled transition in the opposite direction from the aggressor lines. Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.

• 한국레이저가공학회지
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• 제13권4호
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• pp.7-13
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• 2010

Today, the most common process for generating Through Silicon Vias (TSVs) for 3D ICs is Deep Reactive Ion Etching (DRIE), which allows for high aspect ratio blind holes with low surface roughness. However, the DRIE process requires a vacuum environment and the use of expensive masks. The advantage of using lasers for TSV drilling is the higher flexibility they allow during manufacturing, because neither vacuum nor lithography or masks arc required and because lasers can be applied even to metal and to dielectric layers other than silicon. However, conventional nanosecond lasers have the disadvantage of causing heat affection around the target area. By contrast, the use of a picosecond laser enables the precise generation of TSVs with less heat affected zone. In this study, we conducted a comparison of thermalization effects around laser-drilled holes when using a picosecond laser set for a high pulse energy range and a low pulse energy range. Notably, the low pulse energy picosecond laser process reduced the experimentally recast layer, surface debris and melts around the hole better than the high pulse energy process.

• ETRI Journal
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• 제34권5호
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Journal of the Optical Society of Korea
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• 제18권5호
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• pp.531-537
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• 2014

Through-silicon vias (TSVs) are fine, deep holes fabricated for connecting vertically stacked wafers during three-dimensional packaging of semiconductors. Measurement of the TSV geometry is very important because TSVs that are not manufactured as designed can cause many problems, and measuring the critical dimension (CD) of TSVs becomes more and more important, along with depth measurement. Applying white-light scanning interferometry to TSV measurement, especially the bottom CD measurement, is difficult due to the attenuation of light around the edge of the bottom of the hole when using a low numerical aperture. In this paper we propose and demonstrate four bottom CD measurement methods for TSVs: the cross section method, profile analysis method, tomographic image analysis method, and the two-dimensional Gaussian fitting method. To verify and demonstrate these methods, a practical TSV sample with a high aspect ratio of 11.2 is prepared and tested. The results from the proposed measurement methods using white-light scanning interferometry are compared to results from scanning electron microscope (SEM) measurements. The accuracy is highest for the cross section method, with an error of 3.5%, while a relative repeatability of 3.2% is achieved by the two-dimensional Gaussian fitting method.

• Journal of Welding and Joining
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• 제31권6호
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• 대한금속재료학회지
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• 제48권11호
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• 전자통신동향분석
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• 제25권5호
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• pp.97-105
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• 2010

모바일과 유비쿼터스 센서 네트워크 센서 시대가 도래함에 따라 가볍고, 작고, 얇고, 멀티기능을 구현할 수 있는 부품에 대한 요구가 증대하고 있다. 이에 대한 여러 가지 솔루션 중 MCM의 개념을 수직 방향으로 확장시킨 3D IC가 최근 각광을 받고 있다. 이는 물리적인 한계에 부딪힌 반도체 집적 공정의 한계를 극복하여 지속적으로 무어의 법칙에 맞춰 집적도를 향상시킬 수 있을 뿐만 아니라 소재와 공정이 달라도 3차원적으로 집적이 가능하여 메모리와 프로세서로 대표되는 디지털 칩뿐만 아니라 아날로그/RF, 수동소자, 전력소자, 센서/액추에이터, 바이오칩 등을 하나로 패키징 할 수 있는 장점이 있기 때문이다. 이를 통해 성능 향상, 경박단소, 저비용의 부품 개발이 가능하기 때문에 미국, 유럽, 일본 등 선도국뿐만 아니라 싱가포르, 타이완, 중국 등에서도 활발한 연구가 진행되고 있으며 CMOS 이미지 센서 모듈 생산에 TSV 기술이 이미 적용되고 있다. 본 고에서는 3D IC를 위한 TSV 및 적층 요소 기술을 소개하고 이를 통해 개발된 사례와 표준화 동향에 대하여 소개하고자 한다.

• 한국어병학회지
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• 제33권1호
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• pp.71-75
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• 2020

A survey was conducted to investigate viral infections in 184 whiteleg shrimp (Litopenaeus vannamei) collected from nine farms and one wholesale fish vendor during 2018 and 2019. Gill and abdominal muscle of shrimp were tested for the presence of five viruses, viz. infectious hypodermal and haematopoietic necrosis virus, taura syndrome virus, infectious myonecrosis virus, yellow head virus genotype 1, and covert mortality nodavirus by reverse transcription-polymerase chain reaction (RT-PCR) and PCR. These viruses were not detected in any of 184 samples, screened under the study.

• Journal of information and communication convergence engineering
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• 제12권1호
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• 한국정밀공학회지
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• 제26권12호
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• pp.9-17
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• 2009