Novel Bumping and Underfill Technologies for 3D IC Integration |
Sung, Ki-Jun
(Convergence Components & Materials Research Laboratory, ETRI, Package Design Technology Team of SK Hynix Semiconductor)
Choi, Kwang-Seong (Convergence Components & Materials Research Laboratory, ETRI) Bae, Hyun-Cheol (Convergence Components & Materials Research Laboratory, ETRI) Kwon, Yong-Hwan (Convergence Components & Materials Research Laboratory, ETRI) Eom, Yong-Sung (Convergence Components & Materials Research Laboratory, ETRI) |
1 | K. Sakuma et al., "Fluxless Bonding for Fine-Pitch and Low-Volume Solder 3-D Interconnections," Proc. Electron. Compon. Technol. Conf., May 2011, pp. 7-13. |
2 | Z.-Q. Zhang, S.H. Shi, and C.P. Wong, "Development of No-Flow Underfill Materials for Lead-Free Solder Bumped Flip-Chip Applications." IEEE Trans. Compon. Packag. Technol., vol. 24, no. 1, 2001, pp. 59-66. DOI ScienceOn |
3 | J. -W. Nah et al., "Development of Wafer Level Underfill Materails and Assembly Processes for Fine Pitch Pb-Free Solder Flip Chip Packaging," Proc. Electron. Compon. Technol. Conf., May 2011, pp. 1015-1022. |
4 | S. Katsurayama et al., "High Performance Wafer Level Underfill Material with High Filler Loading," Proc. Electron. Compon. Technol. Conf., May 2011, pp. 370-374. |
5 | M. Lee et al., "Study of Interconnection Process for Fine Pitch Flip Chip," Proc. Electron. Compon. Technol. Conf., May 2009, pp. 720-723. |
6 | Y.-S. Eom et al., "Characterization of Polymer Matrix and Low Melting Point Solder for Anisotropic Conductive Film," Microelectron. Eng., vol. 85, no. 2, 2008, pp. 327-331. DOI ScienceOn |
7 | Y.-S. Eom et al., "Electrical Interconnection with a Smart ACA Composed of Fluxing Polymer and Solder Powder," ETRI J., vol. 32, no. 3, June, 2010, pp. 414-421. DOI ScienceOn |
8 | Y.-S. Eom et al., "Characterization of a Hybrid Cu Paste as an Isotropic Conductive Adhesive," ETRI J., vol. 33, no. 6, Dec. 2011, pp. 864-870. DOI |
9 | P.G. Emma and E. Kursun, "Is 3D Chip Technology the Next Growth Engine for Performance Improvement?" IBM J. Res., Dev., vol. 52, no. 6, Nov. 2008, pp. 541-552. DOI |
10 | P. Ramm et al., "3D Integration Technology: Status and Application Development," Proc. ESSCIRC, Sept. 2010, pp. 9-16. |
11 | J.H. Lau, "Evolution and Outlook of TSV and 3D IC/Si Integration," Proc. Electron. Packag. Technol. Conf., Dec. 2010, pp. 560-570. |
12 | B. Dang et al., "3D Chip Stacking with C4 Technology," IBM J. Res. Dev., vol. 52, no. 6, Nov. 2008, pp. 599-609. DOI |
13 | K. Sakuma et al., "3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-Free Interconnections," IBM J. Res. Dev., vol. 52, no. 6, Nov. 2008, pp. 611-622. DOI |
14 | J. Hwang et al., "Fine Pitch Chip Interconnection Technology for 3D Integration," Proc. Electron. Compon. Technol. Conf., June 2010, pp. 1399-1403. |
15 | J.U. Knickerbocker et al., "3D Silicon Integration," Proc. Electron. Compon. Technol. Conf., May 2008, pp. 538-543. |
16 | R. Agarwal et al., "Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking," Proc. Electron. Compon. Technol. Conf., June 2010, pp. 858-863. |
17 | R. Lathrop, "Semiconductor Packaging Solutions Utilizing Fine Powder Solder Paste," Proc. Int. Wafer-Level Packag. Conf., 2008, pp. 129-136. |
18 | M. Gerber, "Next Generation Fine Pitch Cu Pillar Technology-Enabling Next Generation Silicon Nodes," Proc. Electron. Compon. Technol. Conf., May 2011, pp. 612-618. |
19 | K.-S. Choi et al., "Novel Maskless Bumping for 3D Integration," ETRI J., vol. 32, no. 2, Apr. 2010, pp. 342-344. DOI ScienceOn |
20 | K.-S. Choi et al., "Novel Bumping Material for Solder-on-Pad Technology," ETRI J., vol. 33, no. 4, Aug. 2011, pp. 637-640. DOI ScienceOn |