• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.60-64
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• 2023

In this study, the electrical contact resistance characteristics between graphene and metals, which is one of important factors for the performance of graphene-based devices, were compared. High-quality graphene was synthesized by chemical vapor deposition (CVD) method, and Al, Cu, Ni, and Ti as electrode materials were deposited on the graphene surface with equal thickness of 50 nm. The contact resistances of graphene transferred to SiO₂/Si substrates and metals were measured by the transfer length method (TLM), and the average contact resistances of Al, Cu, Ni, and Ti were found to be 345 Ω, 553 Ω, 110 Ω, and 174 Ω, respectively. It was found that Ni and Ti, which form chemical bonds with graphene, have relatively lower contact resistances compared to Al and Cu, which have physical adsorption properties. The results of this study on the electrical properties between graphene and metals are expected to contribute to the realization of high-performance graphene-based devices including electronics, optoelectronic devices, and sensors by forming low contact resistance with electrodes.

• ETRI Journal
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• v.27 no.5
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• Korean Journal of Materials Research
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• v.7 no.11
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• pp.1018-1023
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• 1997

본 연구에서는 3C-SiC의 ohmic 접합에 대하여 그 전기적 특성과 미세구조의 상관관계에 대하여 분석하였다. 표준사진식각 공정을 통하여 ohmic접합 금속으로서 Ni을 진공증착시켜 일련의 TLM패턴으로 열처리에 따르는 전류-전압 특성을 조사하였고 TEM, SEM, AES, EDS를 사용하여 Ni/SiC 계면에 대한 미세구조, 화학적 특성을 분석하였다. 열처리 온도와 시간을 통한 thermal budget이 증가함에 따라서 접촉저항이 감소되었으며 그 값은 $10^{-2}$-$10^{-4}$Ω$\textrm{cm}^2$의 범위에 속하였다. EDS와 AES를 통하여 7$50^{\circ}C$이상의 열처리 후 silicide(NiSi$_{2}$)의 주변에 carbon층이 형성되는 것을 확인하였으며, 열처리 온도가 증가함에 따라서 island형 silicide의 크기가 조밀해지며 SiC와의 접착성이 향상됨을 알 수 있었다. Ni/3C-SiC ohmic 접합의 전기적 특성은 계면에 생성되는 silicide와 carbon의 형성거동에 의하여 결정되는 것으로 믿어진다.

• Journal of information and communication convergence engineering
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• v.8 no.2
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• pp.163-167
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• 2010

In underwater acoustic communication, acoustic signals from transducers or hydrophones are used. And the underwater acoustic communication channels are very complicated, because of vertical distribution of acoustic velocity according depths, and reflections from boundaries like as surface or bottom. For the implementation of the underwater acoustic communication channel, the image method or ray tracing method have been used. In this paper, we introduce a new approach for implementation of underwater acoustic communication channel using the simulation of the Transmission Line Matrix Modeling and cross-correlations from the input and output signals.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.11a
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• pp.175-180
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• 2006

The acoustical properties of multi-layered treatments of materials used in applications, such as automotive liners, generally cannot be directly measured by a one-time test in a standing wave duct. Therefore, we have to consider predicting them by the four-pole transfer matrix method. This method requires performing TCM or TLM for measuring the transfer matrix of each layer and calculating the total transfer matrix of the whole multi-layered material. The final predicted absorption ratios and transmission losses of the multi-layered treatments strongly depend on the measured transfer matrix of each layer. All these functions have been included in a new designed acoustical software.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.25-26
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• 2011

In this paper, we investigated the effect of various annealing processes on the electrical characteristics of oxide thin film transistors (TFTs). When we annealed the TFT devices before and after source/drain (S/D) process, we could observe the different electrical characteristics of oxide TFTs. When we annealed the TFTs after deposition of transparent indium zinc oxide S/D electrodes, the annealing process decreased the contact resistance but increased the resistivity of S/D electrodes. The field effect mobility, subthreshold slope and threshold voltage of the oxide TFTs annealed before and after S/D process were 5.83 and 4.47 $cm^2$/Vs, 1.20 and 0.82 V/dec, and 3.92 and 8.33 V respectively. To analyze the differences, we measured the contact resistances and the carrier concentrations using transfer length method (TLM) and Hall measurement.

• Korean Journal of Veterinary Research
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• v.35 no.4
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• pp.809-814
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• 1995

The acute and subacute toxicity of fumomsin $B_1$ was evaluted in fingerlings of common carp, Cyprinus carpio. Dipping of fish for acute toxicity was performed for a period of 48 hours, and the $TLm_{48h}$ value(median tolerance limit) was more than 1000 ppm in common carp. Severe damages were observed in various organs and among them, clubbing of gill lamella, lytic degeneration and vacuolation of liver cells, and epithelial edema of renal tubules were relatively prominent. The most significant changes were hyperbasophilic foci of liver cells in subacute toxicity test and these can imply the possibility of hepatocarcinogenecity of fumonisin $B_1$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.33-36
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• 2004

탄소 도핑$(5{\times}10^{19}\;cm^{-3})$된 p-type GaAsSb 에피층 위에, Ti/Pt/Au, Pd/Au, Pd/Ir/Au를 이용한 다층 오믹 접촉을 제작하였다. MOCVD(metal-organic chemical vapor deposition)를 이용하여 성장시킨 이 p-GaAsSb의 정공 이동도는 탄소의 도핑 농도가 매우 높음에도 불구하고, $50\;cm^2/Vs$로 측정되었다. 오믹 접촉의 전기적 특성을 측정하기 위하여 TLM(Transfer length method)를 이용하였다. Pd/Ir/Au을 이용한 오믹접촉의 specific contact resistivity는 $10^{-8}\;ohm-cm^2$ 보다 작은 수치를, transfer length는 100 nm보다 작은 수치를 보였으며, Ti/Pt/Au을 이용한 ohmic contact의 specific contact resistivity는 $10^{-7|\;ohm-cm^2$ 보다 작은 수치를, transfer length는 400 nm보다 작은 수치를 나타내었다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.561-562
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• 2008

In this paper, we propose a establishment of system level environment to exploit PC system with SSD (Solid State Disk) by using TLM (Transaction Level Modeling) method with SystemC language. The reason why we choose this modeling method is that it eases RTL (Register Transfer Level) modeling burdens and we can accurately estimate the performance about different architectural changes. Also, it provides simulation speed which is relatively faster than RTL modeling method. The baseline architectural platform we implemented showed that SSD's internal transfer time is a dominant factor, so we need to improve that part and it is expected to be a good simulator to measure the system's overall performance by exploiting SSD's internal architectures.