• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.393-394
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• 2004

To get rid of cell assembly margin and have more process room of upper substrate, we developed truly COT (Color Filter On TFF Array) LCDs in that B/M (Black Matrix) as well as C/F (Color Filter) layer is located on TFT substrate. Novel B/M material is also developed for this COT structure. Difficulty in making contact hole through C/F layer was solved by making each C/F pattern isolated from others. We think this configuration will be core technology for prominent COT LCDs.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.601-604
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• 2006

We have developed ZnO TFT array using conventional photolithography and wet etching processes. Transparent 20 nm of ultra thin ZnO film deposited by means of plasma enhanced atomic layer deposition at $100^{\circ}C$ was used for the active channel. The ZnO TFT has a mobility of $0.59cm^2/V.s$, a threshold voltage of 7.2V, sub-threshold swing of 0.64V/dec., and an on/off ratio of $10^8$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.977-982
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• 2007

The realization of the photoresist(PR) removal method with vaporized water and ozone gas mixture has been studied for the LCD TFT array manufacturing. The developed PR stripper uses the water boundary layer control method based on the high concentration ozone production technology. We develop the prototype of PR stripper and experiment to find the optimal process parameter condition like as the ozone gas flow/concentration, process reaction time and thin boundary layer formation. As a results, we realize the LCD PR strip rate over the 0.4 ${\mu}m/min$ and this PR removal rate is more than 5 times higher than the conventional immersion type ozonized water process.

• The Optical Journal
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• s.108
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• pp.41-43
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• 2007

경희대학교 차세대 디스플레이연구센터(센터장.장진, http://adrc.khu.ac.kr)에서는 산업자원부의 산업기술기반조성사업을 통해 박막 트랜지스터용 박막재료와 이를 이용한 TFT 및 TFT-array를 제조할 수 있는 핵심공정장비와 기술을 구축하고 산학연의 연구.개발 지원, 디스플레이 부품.재료의 성능평가 및 연구인력 양성과 더불어 신기술 분야에 대한 연구를 수행하고 있다. 100억원의 막대한 설비투자를 통해 디스플레이 R&D 인프라를 구축하고 다양한 성과를 창출하며 전문 연구기관으로 자리매김하고 있는 경희대학교 차세대 디스플레이연구센터를 찾아 그간의 연구성과와 향후 계획에 대해 들어보았다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.13.1-13.1
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• 2009

Transparent electronics has attracted many interests, for it can open new applications for consumer electronics, transportation, business, and military. Among them, display backplane, thin film transistor (TFT) array would be the most attractive application. Many researchers have been investigating oxide semiconductors for transparent channel material of TFT since the report for transparent amorphous oxide semiconductor (TAOS) TFT by Hosono group and ZnO TFT by Wager group. Especially, oxide TFTs have been intensively investigated during a couple of years since the first demonstration of ZnO-TFT driving AM-OLED. Many papers regarding the fabrication and performance of oxide TFTs, and active matrix display driven by oxide TFTs have been reported. Now lots of people have confidence in the competitiveness of oxide TFTs for the backplane of AM-Display. Especially, high mobility, uniformity, fairly good stability, and low cost process make oxide TFTs applied even to a large size AM-OLED. Last year, Samsung mobile display, former SID, reported 12" AM-OLED driven by IZGO-TFT and it seems that the remained issue for the mass production is the bias temperature stability. Here, we will introduce the application of oxide TFT and important issue for oxide TFT to be used for the direct printing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.280.2-280.2
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• 2016

The graphene, a single atomic sheet of graphite, has attracted tremendous interest owing to its novel properties including high intrinsic mobility, optical transparency and flexibility. However, for more diverse application of graphene devices, it is essential to tune its transport behavior by shifting Dirac Point (DP) of graphene. So, in the following context, we suggest a method to tune structural and electronic properties of graphene using atomic layer deposition. By atomic layer deposition of zinc oxide (ZnO) on graphene using 4-mercaptophenol as linker, we can fabricate n-doped graphene. Through ${\pi}-{\pi}$ stacking between chemically inert graphene and 4-mercaptophenol, conformal deposition of ZnO on graphene was enabled. The electron mobility of graphene TFT increased more than 3 times without considerably decreasing the hole mobility, compared to the pristine graphene. Also, it has high air stability. This ZnO doping method by atomic layer deposition can be applicable to large scale array of CVD graphene TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.695-698
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• 2006

The photosensitive poly-siloxane material used as the passivation layers for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been improved by the back channel oxygen treatment and the devices exhibits lower leakage current than the conventional silicon nitride passivation layer of BCE TFTs. The leakage currents between Indium-tin-oxide (ITO) pixels and the TFT devices and its mechanism have also been investigated in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.531-534
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• 2005

This paper presents a new data line sharing technique for TFT-LCD panels. This technique reduces the number of data driver IC's to half by having two adjacent pixels share the same data line. This in turn doubles the number of gate lines, which are integrated directly on the glass substrate of amorphous silicon for further cost reduction and more compactness. The proposed technique with new pixel array structure was applied to 15.4 inch WXGA TFT-LCD panels and has proven that the number of driver IC's were halved with nearly 41% circuit cost reduction and 5.3% reduction in power consumption without degrading the image quality.

• Computers and Concrete
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• v.13 no.3
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• pp.325-342
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• 2014

The use of lightweight aggregate (LWA) instead of ordinary aggregate may make lightweight aggregate concrete, which possesses many advantages such as lightweight, lower thermal conductivity, and better fire and seismic resistance. Recently the developments of LWA have been focused on using industrial wastes as raw materials to reduce the use of limited natural resources. In view of this, the intent of this study was to apply Taguchi optimization technique in determining process condition for producing synthetic LWA by incorporating waste thin film transition liquid crystal displays (TFT-LCD) glass powder with reservoir sediments. In the study the waste TFT-LCD glass cullet was used as an additive. It was incorporated with reservoir sediments to produce LWA. Taguchi method with an orthogonal array L16(45) and five controllable 4-level factors (i.e., cullet content, preheat temperature, preheat time, sintering temperature, and sintering time) was adopted. Then, in order to optimize the selected parameters, the analysis of variance method was used to explore the effects of the experimental factors on the performances (particle density, water absorption, bloating ratio, and loss of ignition) of the produced LWA. The results showed that it is possible to produce high performance LWA by incorporating waste TFT-LCD glass cullet with reservoir sediments. Moreover, Taguchi method is a promising approach for optimizing process condition of synthetic LWA using recycled glass cullet and reservoir sediments and it significantly reduces the number of tests.