• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Electronics and Telecommunications Trends
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• v.24 no.6
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• pp.94-98
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• 2009

최근 모바일 멀티미디어 기기들의 사용이 증가하면서 고성능 멀티미디어 프로세서에 대한 필요성이 높아지고 있는 추세이다. DSP 기반의 시스템은 범용성에 기인하여 다양한 응용 분야에서 사용될 수 있으나 주문형반도체 보다 높은 가격과 전력소모 그리고 낮은 성능을 가진다. ASIP는 주문형반도체의 저비용, 저전력, 고성능과 범용 프로세서의 유연성이 결합된 새로운 형태의 프로세서로서, 단일 칩 상에 H.264, VC-1, AVS, MPEG 등과 같은 다양한 멀티미디어 비디오 표준 및 OFDM과 같은 통신 시스템을 지원하고 또한 고성능의 처리율과 계산량을 요구하는 차세대 비디오 표준의 구현을 위한 효과적인 해결책으로 주목되고 있다. 본 기술 문서에서는 ASIP의 특징과 애플리케이션의 가속 방법, ASIP을 위한 컴파일러 설계 및 응용에 관하여 기술한다.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1081-1084
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• 2003

Structural morphology, annealing behavior and dielectric properties of polyaniline-emeraldine base (Pani-EB) and poly methyl methacrylate (PMMA) thin films prepared by spin coating technique have been studied. MIM and MISM structures were used to investigate annealing and dielectric behavior. The XRD and AFM spectrum of as grown and annealed thin films indicates the amorphous nature. The observed amorphous phase, low loss, dielectric behavior and thermal stability even at high temperatures implies the feasibility of utilizing PMMA and Pani-EB thin films as gate dielectric insulator layer in organic thin film transistors which can find application in flat panel display.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Surface Science and Engineering
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• v.40 no.2
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• pp.98-102
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• 2007

[ $NiCl_2$ ] and poly-L-lysine coated protein chip plates have been fabricated using a spin coating system. Water has been used as solvent and scratching effects on glass slides and ITO have been investigated. We also observed the surface properties of $NiCl_2$ and poly-L-lysine coated slides by using PSA(Particle size analyzer) and AFM(Atomic force microscope). The AFM results imply that the surface patterns created in the spin coating system determine the protein adsorption. Adsorption of histidine-tagged KRS proteins immobilized on glass slides and ITO was analyzed using a BAS image system. The results suggest that the scratching effect was increased ability of protein adsorption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1128-1133
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• 2008

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interactions. This paper proposes a context-aware system architecture to be implemented on an UoC (Ubiquitous system on Chip). A new proposed technology of CRS (Context Recognition Switch) and DOS (Dynamic and Optimal Standard) based on Context-awareness system architecture with pre-processor, HPSP(High Performance Signal Processor) in this paper. And proposed a new algorithm using in network topology processor shows for Ubiquitous Computing System. implementing in UoC (Ubiquitous System on Chip) base on the IEEE 802.15.4 WPAN (Wireless Personal Area Network) standard. Also, This context-aware based UoC architecture has been developed to apply to mobile intelligent robots which would support human in a context-aware manner.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.190-193
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• 2009

The most essential element in wireless sensor network is wireless sensor node which collects environmental information and transmits it to the user application systems. Recently, due to the technological advancement, wireless sensor nodes are become smaller, more intelligent and less power consuming. Especially, SoC(System-on-Chip) technology, which unifies the MCU, RF module, memory and other element inside one chip, plays an important part for miniaturization of sensor node, hence reduces the manufacturing expenses. In this paper, we have designed a miniaturized wireless sensor node for wireless sensor network using commercial SoC technology and discussed about some application scenario and additional considerations.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2212-2215
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• 2003

In this paper, we proposed speech feature vector extractor for embedded system using TMS 320C31 DSP chip. For this extractor, we used algorithm using cepstrum coefficient based on LPC(Linear Predictive Coding) that is reliable algorithm to be is widely used for speech recognition. This system extract the speech feature vector in real time, so is used the mobile system, such as cellular phones, PDA, electronic note, and so on, implemented speech recognition.