• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.112-117
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• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.55-60
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• 2010

For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.

• Journal of the Korean Society for Railway
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• v.17 no.5
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• pp.349-354
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• 2014

Other foreign countries already apply ETCS LEVEL 2 in signaling systems. It provides added functions to control a train using wireless communication compared with ETCS LEVEL 1. Nowadays, the ETCS LEVEL 2 system is being applied on revenue services more and more frequently. Therefore, it is necessary to develop ETCS LEVEL 2 to apply in this country. The advanced technology of the ETCS LEVEL 2 system provides continuous control for train protection, and ATP function, by comparing discontinuous controls on ETCS LEVEL 1. ETCS LEVEL 2 is a better system model for improving passenger safety. This paper describes the design of an onboard speed profile for the ETCS LEVEL 2 system and it forecasts the future of ETCS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Journal of the Korea Society for Simulation
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• v.26 no.2
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• pp.41-49
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• 2017

In the acquisition program, the conceptual design is the most important step toward specifying the military objectives, establishing requirements and determining future developmental directions, of a target system. However, if both the requirements and directions are incorrectly set due to the lack of development experiences and literature backgrounds in the target systems, such as future ground combat vehicles, it may become a major risk in the future design phases and the entire acquisition program. In order to correct these errors in the future phases, time, effort and cost are required. Therefore, it is necessary to reduce the errors that occur in the initial stages to effectively acquire the future ground combat vehicles. This paper describes the initial design method for verifying the requirements and the developmental directions and estimating the system performance at the conceptual design through the system-level physical modeling and simulation (M&S) and the target system performance analysis. The system-level physical M&S use cutting-edge design tools, model-based designs and geometric-based designs. The system performance estimation is driven from the results of the system-level physical M&S and the specialized system analysis software.

• Nuclear Engineering and Technology
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• v.32 no.2
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• pp.157-168
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• 2000

The nuclear steam generator level control system is designed by robust control methods. The feedwater controller is designed by three methods of the H$\infty$, the mixed weight sensitivity and the structured singular value. Then the controller located on the feedback loop of the level control system is designed. For the system performance, the controller of simple PID whose coefficients vary with the power is selected. The simulations show that the system has a good performance with proper stability margins.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Journal of the Earthquake Engineering Society of Korea
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• v.18 no.3
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• pp.141-150
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• 2014

A methodology to evaluate the seismic performance of interface piping systems that cross the isolation interface in the seismically isolated nuclear power plant (NPP) was developed. The developed methodology was applied to the safety-related interface piping system to demonstrate the seismic performance of the target piping system. Not only the seismic performance for the design level earthquakes but also the performance for the beyond design level earthquakes were evaluated. Two artificial seismic ground input motions which were matched to the design response spectra and two historical earthquake ground motions were used for the seismic analysis of piping system. The preliminary performance evaluation results show that the excessive relative displacements can occur in the seismically isolated piping system. If the input ground motion contained relatively high energy in the low frequency region, we could find that the stress response of the piping system exceed the allowable stress level even though the intensity of the input ground motion is equal to the design level earthquake. The structural responses and seismic performances of piping system were varied sensitively with respect to the intensities and frequency contents of input ground motions. Therefore, for the application of isolation system to NPPs and the verification of the safety of piping system, the seismic performance of the piping system subjected to the earthquake at the target NPP site should be evaluated firstly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.9
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• pp.1822-1830
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• 2002

The paper describes the development of a decomposition based multidisciplinary design optimization (MDO) method that coordinates each of disciplinary subspace optimization (DSO). A multidisciplinary design system considered in the present study is decomposed into a number of subspaces based on their own design objective and constraints associated with engineering discipline. The coupled relations among subspaces are identified by interdisciplinary design variables. Each of subsystem level optimization, that is DSO would be performed in parallel, and the system level coordination is determined by the first order optimal sensitivities of subspace objective functions with respect to interdisciplinary design variables. The central of the present work resides on the formulation of system level coordination strategy and its capability in decomposition based MDO. A fluid-structure coupled design problem is explored as a test-bed to support the proposed MDO method.