• 제어로봇시스템학회논문지
• /
• 제10권1호
• /
• pp.73-80
• /
• 2004

We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• 융합신호처리학회논문지
• /
• 제9권1호
• /
• pp.89-97
• /
• 2008

전동기의 카오스 현상은 실시간 구현에 있어 바람직하지 않은 동특성으로서, 일반적으로 정상상태에서 전동기 속도가 진동을 한다든지 토크가 랜덤하게 변하는 특징이 있다. 본 논문은 카오스 현상을 갖는 영구자석형 동기 전동기의 적응제어기법을 제안한다. 전동기의 계수(parameter)는 어느 범위 안에서 랜덤하게 변화하는 시변특성을 갖는다. 제어기 설계는 우선, 전동기의 비선형 시스템 모델을 공칭 선형시스템 이론을 적용하여 선형화한다. 또한 실시간에서 시스템 계수의 변화로 인해 발생하는 제어오차를 보상하기 위한 보조제어기법을 제안하며 리아푸노브 안정성 이론을 적용하여 그 제어규칙을 산출한다. 컴퓨터 시뮬레이션을 통하여 제안한 제어기법의 타당성 및 신뢰성을 검증하며 기존의 제어기법과 비교 분석하여 성능의 우수성을 입증하였다. 또한 PSoC(Programmable System-on-Chip)기반 구동 드라이브를 포함하는 실시간 전동기의 제어시스템 실험을 통해 실제 적용가능성을 검증한다.

• Journal of information and communication convergence engineering
• /
• 제2권2호
• /
• pp.76-79
• /
• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• 한국원자력학회:학술대회논문집
• /
• 한국원자력학회 1996년도 추계학술발표회논문집(1)
• /
• pp.191-196
• /
• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• Journal of information and communication convergence engineering
• /
• 제15권3호
• /
• pp.151-159
• /
• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• 전기전자학회논문지
• /
• 제17권3호
• /
• pp.241-247
• /
• 2013

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
• /
• pp.563-566
• /
• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.

• 대한전자공학회논문지SD
• /
• 제44권12호
• /
• pp.61-70
• /
• 2007

메모리 기술이 발달함에 따라 메모리의 집적도가 증가하게 되었고, 이러한 변화는 구성요소들의 크기를 작아지게 만들고, 고장의 감응성이 증가하게 하였다. 그리고 고장은 더욱 복잡하게 되었다. 또한, 칩 하나에 포함되어있는 저장 요소가 늘어남에 따라 테스트 시간도 증가하게 되었다. 그리고 SOC 기술의 발달로 대용량의 내장 메모리를 통합할 수 있게 되었지만, 테스트 과정이 복잡하게 되어 외부 테스트 환경에서는 내장 메모리를 테스트하기 어렵게 되었다. 본 논문에서 제안하는 테스트 구조는 내장 테스트를 사용하여 외부 테스트 환경 없이 테스트가 가능하다. 제안하는 내장 테스트 구조는 다양한 알고리즘을 적용 가능하므로, 생산 공정의 수율 변화에 따른 알고리즘 변화에 적용이 가능하다. 그리고 메모리에 내장되어 테스트하므로, At-Speed 테스트가 가능하다. 즉, 다양한 알고리즘과 여러 형태의 메모리 블록을 테스트 가능하기 때문에 높은 효율성을 가진다.

• 전력전자학회논문지
• /
• 제16권2호
• /
• pp.97-104
• /
• 2011

본 논문은 건물 내에서 발생되는 각종 화재 및 재해를 자동으로 신속히 감지한 후 현지에 설치된 방재설비들을 자동으로 동작시켜 화재 및 재해를 초기진압하고, 이들 재해상황들을 유무선 통신망을 통하여 실시간으로 원격지 상황실의 중앙관리시스템에서 모니터링되는 고속 고정밀의 IT 기반의 방재용 자동화시스템을 개발한다. 본 논문에서 제안하는 방재용 자동화시스템은 소형.경량 및 고감도 고정밀의 원칩형 PLC (one-chip type PLC)가 적용되어, 각종 재해 센서로부터 감지된 신호를 분석하고 재해발생시 조기진압을 위한 현장의 방재용 구동장치들을 작동시킨다. 또한 검출된 데이터들은 RS232c 및 블루투스에 의한 유무선 통신망을 통해 원격지 상황실에 데이터 전송 및 긴급 경보신호를 송출시키고, 모니터링 프로그램을 구동시킨다. 제안한 IT 기반의 방재용 자동화시스템은 화재와 각종 재해에 대한 예방과 신속한 조치로 인명과 재산의 손실을 최소화 하고자 한다.

• Journal of Magnetics
• /
• 제16권4호
• /
• pp.363-367
• /
• 2011

We have designed, fabricated and demonstrated a novel micro-system for programmable magnetic actuation using magnetic elliptical pathways on Si substrates. Lithographically patterned soft NiFe ellipses are arranged sequentially perpendicular to each other as stepping stones for the transport of magnetic beads. We have measured the magnetization curve of the ellipsoid ($9\;{\mu}m{\times}4\;{\mu}m{\times}0.1\;{\mu}m$) elements with respect to the long and short axes of the ellipse. We found that the magnetization in the long axis direction is larger than that in the short axis direction for an applied field of ${\leq}$ 1,000 Oe, causing a force on carriers that causes them to move from one element to another. We have successfully demonstrated a micro-system for the magnetic actuation of biomolecule carriers of superparamagnetic beads (Dynabead$^{(R)}$ 2.8 ${\mu}m$) by rotating the external magnetic field. This novel concept of magnetic actuation is useful for future integrated lab-on-a-chip systems for biomolecule manipulation, separation and analysis.