• 제목/요약/키워드: System on a Chip

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임베디드 스마트 응용을 위한 신경망기반 SoC (A SoC Based on a Neural Network for Embedded Smart Applications)

  • 이봉규
    • 전기학회논문지
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    • 제58권10호
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    • pp.2059-2063
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    • 2009
  • This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

효율적인 네트워크 사용을 위한 온 칩 네트워크 프로토콜 (On-chip-network Protocol for Efficient Network Utilization)

  • 이찬호
    • 대한전자공학회논문지SD
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    • 제47권1호
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    • pp.86-93
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    • 2010
  • 반도체 공정 및 설계 기술의 발전에 따라 SoC에 보다 많은 기능이 포함되고 데이터 전송량 또한 급격히 증가하고 있다. 이에 따라 SoC 내부의 온 칩 네트워크에서 데이터 전송 속도가 전체 시스템의 성능에 큰 영향을 미치게 되어 이와 관련된 연구가 활발하게 진행되고 있다. 기존의 AHB를 대체하기 위한 온 칩 네트워크 프로토콜로 AXI와 OCP가 대표적으로 거론되고 있으나 전송 성능을 증가시키기 위해 신호선의 수가 크게 증가하여 인터페이스와 네트워크 하드웨어 설계가 매우 어렵고 기존에 널리 사용되던 AHB와 다른 프로토콜과의 호환성도 좋지 않다. 본 논문에서는 이를 개선하기 위한 새로운 온 칩 네트워크 프로토콜을 제안한다. 제안된 프로토콜은 신호선의 수를 기존의 AHB보다 줄이고 AXI 등 다른 프로토콜과의 호환성도 고려하였다. 성능 분석결과 AXI보다는 조금 떨어지는 성능을 보여주고 있으나 8-버스트 이상의 전송에서는 큰 차이가 없고 신호선 수대비 성능에서는 월등히 우수함을 확인하였다.

Method of Ga removal from a specimen on a microelectromechanical system-based chip for in-situ transmission electron microscopy

  • Yena Kwon;Byeong-Seon An;Yeon-Ju Shin;Cheol-Woong Yang
    • Applied Microscopy
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    • 제50권
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    • pp.22.1-22.6
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    • 2020
  • In-situ transmission electron microscopy (TEM) holders that employ a chip-type specimen stage have been widely utilized in recent years. The specimen on the microelectromechanical system (MEMS)-based chip is commonly prepared by focused ion beam (FIB) milling and ex-situ lift-out (EXLO). However, the FIB-milled thin-foil specimens are inevitably contaminated with Ga+ ions. When these specimens are heated for real time observation, the Ga+ ions influence the reaction or aggregate in the protection layer. An effective method of removing the Ga residue by Ar+ ion milling within FIB system was explored in this study. However, the Ga residue remained in the thin-foil specimen that was extracted by EXLO from the trench after the conduct of Ar+ ion milling. To address this drawback, the thin-foil specimen was attached to an FIB lift-out grid, subjected to Ar+ ion milling, and subsequently transferred to an MEMS-based chip by EXLO. The removal of the Ga residue was confirmed by energy dispersive spectroscopy.

칩 마운트 시스템의 진동 경감 (Vibration Reduction of Chip-Mount System)

  • 임경화;장헌탁
    • 한국소음진동공학회논문집
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    • 제11권8호
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    • pp.331-337
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    • 2001
  • The purpose of this study is to analyze the principal causes of vibration problem and find out the method of vibration reduction in a chip-mount system. The principal causes are investigated through measurements of vibration spectrum and model parameters. Modal parameters are obtained by using an experimental model test. Based on the model parameters from experiments. a model of finite element method is formulated. The model presents effective redesign of increasing the natural frequencies in order to reduce the vibration of a chip-mount system. Further, through computer simulation for the behavior of head to be main vibration source, the best acceleration pattern of head movement can be verified to achieve effective head-positioning and reduce the vibration due to head movement.

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A Low Power Multi-Function Digital Audio SoC

  • Lim, Chae-Duck;Lee, Kyo-Sik
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.399-402
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    • 2004
  • This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

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휴대용 컴퓨터내의 이상유동 냉각시스템을 이용한 모사칩의 열성능에 관한 연구 (A Study on Thermal Performance of Simulated Chip using a Two Phase Cooling System in a Laptop Computer)

  • 박상희;최성대
    • 한국기계가공학회지
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    • 제10권3호
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    • pp.53-59
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    • 2011
  • In this study, a two-phase closed loop cooling system is desinged and tested for a laptop computer using a FC-72. The cooling system is characterized by a parametric study which determines the effects of existence of a boiling enhancement microstructure, initial system pressure, volume fill ratio of coolant and inclination angle of condenser on the thermal performance of the closed loop. Experimental data show the optium condition when the volume ratio of working fluid is 70%, the pump flowing is 6ml/min, and the inclination angle of condenser is $0^{\circ}$. This research shows the maximum values which can dissipate 33W of chip power with a chip temperature maintained at $95^{\circ}C$.

SOC(System-On-a-Chip)에 있어서 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트 (Efficient Test Data Compression and Low Power Scan Testing for System-On-a-Chip(SOC))

  • 박병수;정준모
    • 한국콘텐츠학회논문지
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    • 제5권1호
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    • pp.229-236
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    • 2005
  • System-On-a-Chip(SOC)을 테스트하는 동안에 요구되는 테스트 시간과 전력소모는 SOC내의 IP 코어의 개수가 증가함에 따라서 매우 중요하게 되었다. 본 논문에서는 수정된 스캔 래치 재배열을 사용하여 scan-in 전력소모와 테스트 데이터의 양을 줄일 수 있는 새로운 알고리즘을 제안한다. 스캔 벡터 내의 해밍거리를 최소화하도록 스캔 래치 재배열을 적용하였으며 스캔 래치 재배열을 하는 동안에 스캔 벡터 내에 존재하는 don't care 입력을 할당하여 저전력 및 테스트 데이터 압축을 하였으며 ISCAS 89 벤치마크 외호에 적용하여 모든 경우에 있어서 테스트 데이터를 압축하고 저전력 스캔 테스팅을 구현하였다.

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디지털 보호 계전기 전용 제어 칩 설계 (Design of digital relay controller on a single chip)

  • 서종완;정호성;권기백;서희석;신명철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 A
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    • pp.215-217
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    • 2000
  • Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

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Lab-on-a-Chip for Monitoring the Quality of Raw Milk

  • Choi Jeong-Woo;Kim Young-Kee;Kim Hee-Joo;Lee Woo-Chang;Seong Gi-Hun
    • Journal of Microbiology and Biotechnology
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    • 제16권8호
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    • pp.1229-1235
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    • 2006
  • A lab-on-a-chip (LoC) was designed for simultaneous monitoring of microorganisms, antibiotic residues, somatic cells, and pH in raw milk. The LoC was fabricated from polydimethylsiloxane (PDMS) using microelectromechanical system (MEMS) technology, which consisted of two parts; a protein array and microchannel. The protein array was fabricated by immobilizing five types of antibodies corresponding to two microorganisms, two antibiotic residues, and somatic cells. A sol-gel film was deposited on a glass substrate to immobilize the antibodies. The target analytes in raw milk could be bound with the corresponding antibody by an immunoreaction, and the antigen-antibody complex was detected using fluorescence microscopy. SNARF-dextran was used as a pH indicator, and the SNARF-entrapped hydrogel was attached to the microchannel in the chip. After injecting the milk sample into the channel, the pH was measured by monitoring the change in fluorescence intensity by fluorescence microscopy. The on-chip simultaneous assay of two microorganisms (E. coli O157:H7 and Streptococcus agalactiae), two antibiotic residues (penicillin G and dihydrostreptomycin), and neutrophils was successfully accomplished using the proposed LoC system.

Microfabricated Cell Chip for Cell-based in vitro Assay

  • 박제균;김태한;이상은;김수현;윤규식;이정건
    • 한국생물공학회:학술대회논문집
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    • 한국생물공학회 2000년도 추계학술발표대회 및 bio-venture fair
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    • pp.115-118
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    • 2000
  • 미세 가공 기술을 이용하여 제작된 IDA 전극을 활용하여 임피던스 측정방식의 cell chip으로의 응용에 대해 고찰하였다. IDA 전극은 기존의 반도체 공정으로서 손쉽게 제작할 수 있고, 대량 제작시 전극의 재현성 확보가 용이하고 소형화 할 수 있으며 낮은 단가로 제작될 수 있는 장점이 있다. IDA 전극을 채용한 cell chip을 B16-F1 melanoma 세포 배양에 적용한 결과, 세포성장과 임피던스 변화량이 상관성을 보였고, 세포의 성장을 저해하는 약물의 투과시 cell chip의 임피던스 변화 역시 기존의 방법과 유사한 결과를 보여 주었다.

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