• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1135-1141
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• 2014

Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.2
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• pp.45-51
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• 2006

In this paper, we propose a new architecture of Information Granulation based genetically optimized Self-Organizing Fuzzy Polynomial Neural Networks (IG_gSOFPNN) that is based on a genetically optimized multilayer perceptron with fuzzy polynomial neurons (FPNs) and discuss its comprehensive design methodology involving mechanisms of genetic optimization, especially information granulation and genetic algorithms. The proposed IG_gSOFPNN gives rise to a structurally optimized structure and comes with a substantial level of flexibility in comparison to the one we encounter in conventional SOFPNNs. The design procedure applied in the construction of each layer of a SOFPNN deals with its structural optimization involving the selection of preferred nodes (or FPNs) with specific local characteristics (such as the number of input variables, the order of the polynomial of the consequent part of fuzzy rules, and a collection of the specific subset of input variables) and addresses specific aspects of parametric optimization. In addition, the fuzzy rules used in the networks exploit the notion of information granules defined over system's variables and formed through the process of information granulation. That is, we determine the initial location (apexes) of membership functions and initial values of polynomial function being used in the premised and consequence part of the fuzzy rules respectively. This granulation is realized with the aid of the hard c-menas clustering method (HCM). To evaluate the performance of the IG_gSOFPNN, the model is experimented with using two time series data(gas furnace process and NOx process data).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.9
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• pp.569-574
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• 2020

A floating dock is the main facility for launching ships. In the early 2000s, ship-launching technology using floating docks was developed in Korea. Therefore, the opportunity to participate in new construction projects without investment in dry docks has expanded. In this paper, a basic calculation for the safe mooring of a floating dock was performed, and a mooring system was designed based on this. This study was conducted considering the typhoon situation, which is the most serious environmental requirements of Daebul Pier, a site to be installed and operated, for a floating dock. The design load was calculated by wind load, tidal load, and wave-induced load in accordance with the internationally accepted standards. After performing the initial arrangement of the mooring line of the floating dock using the existing mooring facilities of Daebul Pier, the minimum breaking load for each mooring line was calculated for the given load. Based on the calculation, the mooring arrangement was modified to minimize the breaking load, and a final specification of each mooring line was selected.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.10
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• pp.4865-4885
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• 2019

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line(s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.520-532
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• 2002

A new architecture called the Storage Area Network(SAN) was developed in response to the requirements of high availability of data, scalable growth, and system performance. In order to use SAN more efficiently, most SAN operating systems support storage virtualization concepts that allow users to view physical storage devices attached to SAN as a large volume virtually. A logical volume manager plays a key role in storage virtualization. In order for mapping managers to process snap-shots and reorganizations, an efficient freespace manager is required, and it affects the overall performance of logical volume. In this thesis, we design and implement a freespace manager for logical volume manager. The freespace manager efficiently allocates physical blocks for logical blocks. Also, it processes space allocation requests for supports snapshots and reorganizations.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.155-162
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• 2010

To ensure accurate measurements of wireless network performance, it should be collected real-time data which are transmitted between a large number of nodes in the actual network environment. Therefore, it is necessary to develop simulation tool for finding optimal network system design method such as media access control, routing technique, ad-hoc algorithm of node deployment while overcoming spatial and temporal constraints. Our research attempts to provide an improved architecture and design method of simulation tool for wireless network is an application of multi-threading technique in these issues. We finally show that usability of the proposed simulator by comparing results derived from same test environment in the wireless LAN model of our simulator and widely used network simulation package, NS-2.

• Smart Structures and Systems
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• v.18 no.1
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• pp.75-92
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• 2016

The design of a semi-active (SA) control system addressed to mitigate wind induced structural demand to high wind turbine towers is discussed herein. Actually, the remarkable growth in height of wind turbines in the last decades, for a higher production of electricity, makes this issue pressing than ever. The main objective is limiting bending moment demand by relaxing the base restraint, without increasing the top displacement, so reducing the incidence of harmful "p-delta" effects. A variable restraint at the base, able to modify in real time its mechanical properties according to the instantaneous response of the tower, is proposed. It is made of a smooth hinge with additional elastic stiffness and variable damping respectively given by springs and SA magnetorheological (MR) dampers installed in parallel. The idea has been physically realized at the Denmark Technical University where a 1/20 scale model of a real, one hundred meters tall wind turbine has been assumed as case study for shaking table tests. A special control algorithm has been purposely designed to drive MR dampers. Starting from the results of preliminary laboratory tests, a finite element model of such structure has been calibrated so as to develop several numerical simulations addressed to calibrate the controller, i.e., to achieve as much as possible different, even conflicting, structural goals. The results are definitely encouraging, since the best configuration of the controller leaded to about 80% of reduction of base stress, as well as to about 30% of reduction of top displacement in respect to the fixed base case.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.30 no.2
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• pp.127-135
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• 2017

The computing environment has changed rapidly to enable large-scale finite element models to be analyzed at the PC or workstation level, such as multi-core CPU, optimal math kernel library implementing BLAS and LAPACK, and popularization of direct sparse solvers. In this paper, the design considerations on a parallel finite element code for shared memory based multi-core CPU system are proposed; (1) the use of optimized numerical libraries, (2) the use of latest direct sparse solvers, (3) parallelism using OpenMP for computing element stiffness matrices, and (4) assembly techniques using triplets, which is a type of sparse matrix storage. In addition, the parallelization effect is examined on the time-consuming works through a large scale finite element model.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.