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http://dx.doi.org/10.5515/KJKIEES.2014.25.11.1135

Realtime Wideband SW DDC Using High-Speed Parallel Processing  

Lee, Hyeon-Hwi (Electronic Warfare R&D Lab, LIG Nex1)
Lee, Kwang-Yong (Electronic Warfare R&D Lab, LIG Nex1)
Yun, Sangbom (Electronic Warfare R&D Lab, LIG Nex1)
Park, Yeongil (Agency for Defense Development)
Kim, Seongyo (Agency for Defense Development)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.25, no.11, 2014 , pp. 1135-1141 More about this Journal
Abstract
Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing.
Keywords
Realtime; Wideband DDC SW; Signal Processing; Parallel Processing; CUDA;
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