• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 전력전자학회논문지
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• 제20권3호
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• pp.201-208
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• 2015

The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.

• 전기학회논문지
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• 제64권9호
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• pp.1315-1322
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• 2015

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

• 전기학회논문지
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• 제64권7호
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• 조명전기설비학회논문지
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• 제29권12호
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권8호
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• pp.405-412
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• 2003

This paper presents a three-phase Line-Interactive uninterruptible power supply (UPS) system with series-parallel active power-line conditioning capabilities, using synchronous reference frame (SRF) based controller, which allows an effective power factor correction, source harmonic voltage compensation, load harmonic current suppression, and output voltage regulation. The three-phase UPS system consists of two active power compensator topologies. One is a series active compensator, which works as a voltage source in phase with the source voltage to have the sinusoidal source current and high power factor under the deviation and distortion of the source voltage. The other is a parallel active compensator which works as a conventional sinusoidal voltage source in phase with the source voltage, providing to the load a regulated and sinusoidal voltage with low THD (total harmonic distortion). The control algorithm using SRF method and the active power flow through the Line-interactive UPS systems are described and studied. The simulation and experimental results are depicted in this paper to show the effect of the proposed algorithm.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1137-1145
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• 2017

This paper proposes the dead time effect compensation algorithm using proportional resonant controller in pulse width modulation inverter of motor drive. To avoid a short circuit in the dc link, the dead time of the switch device is surely required. However, the dead time effect causes the phase current distortions, torque pulsations, and degradations of control performance. To solve these problems, the output current including ripple components on the synchronous reference frame and stationary reference frame are analyzed in detail. As a results, the distorted synchronous d-and q-axis currents contain the 6th, 12th, and the higher harmonic components due to the influence of dead time effect. In this paper, a new dead time effect compensation algorithm using proportional resonant controller is also proposed to reduce the output current harmonics due to the dead time and nonlinear characteristics of the switching devices. The proposed compensation algorithm does not require any additional hardware and the offline experimental measurements. The experimental results are presented to demonstrate the effectiveness of the proposed dead time effect compensation algorithm.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1101-1107
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• 2017

In this paper, a robust and fast grid synchronization method of a three-phase power converter is proposed. The amplitude and phase information of grid voltages are essential for power converters to be properly connected into the utility. The phase-lock-loop in synchronous reference frame has been widely adopted for the three-phase converter system since it shows a satisfactory performance under balanced grid voltages. However, power converters often operate under abnormal grid conditions, i.e. unbalanced by grid faults and frequency variations, and thus a proper active and reactive power control cannot be guaranteed. The proposed method adopts a second order generalized integrator in synchronous reference frame to detect positive sequence components under unbalanced grid voltages. The proposed method has a fast and robust performance due to its higher gain and frequency adaptive capability. Simulation and experimental results show the verification of the proposed synchronization algorithm and the effectiveness to detect positive sequence voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1035-1036
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• 2007

This paper presents the characteristics analysis of Interior Permanent Magnet Synchronous Motors(IPMSMs). The development of this program is based on Matlab. In oder to achieve the development of the program, basis algorithm for IPMSMs analysis took advantage of equivalent magnetic circuit analysis technique. The equivalent magnetic circuit analysis for IPMSMs are based on a rotate synchronous d-q reference frame. The mathematical model of the d-q frame voltage equations is used frequently for the analysis of IPMSMs. This program can consider a cross saturation effect and a iron loss and mechanical loss, and provide fast analysis results of IPMSMs characteristics.

• 조명전기설비학회논문지
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• 제21권8호
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• pp.136-143
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• 2007

개선된 지령치 변경부를 가지는 전류제어기는 과도 상태에서의 빠른 응답성과 정상 상태에서의 고정밀도를 가진다. 이 논문에서는 개선된 지령치 변경부가 빠른 과도 응답성을 위하여 동기 PI 제어기를 사용하였다. 전류 제어기의 과도 응답특성은 DC 링크 제어 전압의 부족으로 인해 높은 역기전력 영역에서 많은 문제를 가지고 있다. 이 논문은 지령 전압과 한계 전압을 가지는 개선된 지령치 변경부를 제안하였다.