• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.783-793
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• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.59-62
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• 2000

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.475-476
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• 2007

The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhibitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhibitory state.

• 세라미스트
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• 제21권2호
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1991년도 추계학술대회 논문집
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• pp.1-4
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• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.1-4
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• 1996

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.16-21
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• 2008

본 논문은 새롭게 제안된 단일전자 소자(single-electron device) 및 회로를 이용한 새로운 형태의 홉필드 신경회로망(Hopfield neural network)을 소개한다. 홉필드 신경회로망의 전기적 모델 내부에서 가변저항으로 사용되는 단일전자 시냅스(single-electron synapse)와 비선형 활성함수(nonlinear activation function)로 사용되는 두 단의 단일전자 인버터(single-electron inverter)를 몬테-칼로(Monte-Carlo) 방식의 단일전자 회로 시뮬레이터로 동작을 검증한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.