• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.121-124
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• 2001

This paper proposed resource allocation algorithm for the minimum switching activity of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. The resource allocation method after scheduling use the power function calculating average hamming distance and switching activity of the between two input. First of all, the switching activity is calculated by the input value after calculating the average hamming distance between operation. In this paper, the proposed method though high If level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and max control step. And it is the reduction effect from 6% to 8%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.581-582
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• 2008

This paper describes novel bootstrapped CMOS differential logic family operating at near-Vth supply voltage. The proposed logic family provides improved switching speed by utilizing voltage bootstrapping for the supply voltage approaching device thresholds. The circuit is configured as differential structure having single bootstrapping capacitor, minimizing area overhead and providing complete logic composition capability. A 64-bit adder designed using the proposed technique in a 0.18um CMOS process provides up to 79% improvement in terms of power-delay product as compared to the conventional adder designed with DCVS.

• 전자공학회논문지A
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• 제31A권2호
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• pp.75-80
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• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• 한국지능시스템학회논문지
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• 제9권6호
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• pp.577-582
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• 1999

Using a sole input variable simplifies the design process for the fuzzy logic controller(FLC). This is called single-input fuzzy logic controller(SFLC). However it is still deficient in the capability of adapting to the varying operating conditions. We here design a single-input adaptive fuzzy logic controller(AFLC) using a switching function of the sliding mode control. The AFLC can directly incorporate linguistic fuzzy control rules into the controller. Hence some parameters of the membership functions characterizing the linguistic terms of the fuzzy rules can be adjusted by an adaptive law. In the proposed AFLC center values of fuzzy sets are directly adjusted by a fuzzy logic system. We prove that 1) its closed-loop system is globally stable in the sense that all signals involved are bounded and 2)its tracking error converges to zero asymptotically. We perform computer simulation using a nonlinear plant.

• 전기의세계
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• 제28권1호
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• 한국정보통신학회논문지
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• 제6권8호
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• pp.1283-1291
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• 2002

본 논문에서는 DDFS로 구동하는 PLL을 Q-logic cell based library를 사용하여 schematic 상에서 설계하고 FPGA 0L32$\times$16B를 사용하여 구현하였으며, 측정 결과 주파수 합성기의 스위칭 속도는 DDFS에 사용되는 레지스터 단수와 같다는 결론을 얻을 수 있었다 시뮬레이션 결과 클럭지연은 11클럭 후에 발생되는 것을 알았고, 입력 상태가 랜덤하게 들어온다면 출력에 영향이 있음을 알았다. 따라서 입력상태가 일정간격을 가지게 함으로써 PLL을 구동하기 위한 DDFS는 잡음정형기를 사용하는 것이 좋으며, 또한 D/A 변환기의 대역이 매우 넓어야 하고, PLL의 스위칭 속도보다는 작은 입력 컨트롤 워드의 변화가 바람직하다는 것을 알 수 있다.

• 한국광학회지
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• 제8권6호
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• pp.492-499
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• 1997

굽은 비선형 도파로를 이용한 완전 광 스위치와 굽은 비선형 Y 분기각을 갖는 도파로를 이용한 완전 광 논리 연산소자를 제안하였다. 제안된 완전 광 스위치와 완전 광 논리 연산소자는 굽은 비선형 도파로를 따라가는 비선형파의 전파에 기초를 두고 있다. 빔의 전파특성은 도파로의 비선형성과 입력 파워, 도파로의 굽은 각도 등의 파라미터에 의해 좌우되므로 파라미터를 변화시켜 가면서 파워의 출력 특성을 계산해 보았다. 또한, 비선형 물질로 빠져 나오는 파워를 다양한 위치의 검출기에서 계산함으로써 특정한 검출기의 위치에서 가장 이상적인 디지털 스위칭 특성을 찾았고 도파로 끝과 비선형 물질로 빠져 나오는 파워의 비율에 의해 다양한 논리 함수(AND, OR, XOR)를 구현해 보았다.

• 한국정보통신학회논문지
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• 제9권8호
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• pp.1774-1779
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• 2005

본 논문에서는 그래프 이론에 기초를 둔 GFDD를 사용하여 디지털논리시스템을 구성하는 한가지 방법을 제안하였다. 제안한 방법은 먼저 유한체와 그래프 이론의 수학적 성질을 논의하였으며, 단일변수에 대한 동작영역과 함수영역간의 변환을 용이하게 하기 위한 변환행렬 $\psi$GF(P)(1)과 $\xi$GF(P)(1)을 논의하였다. 그리고 디지털스위칭함수를 구하기 위한 Reed-Muller 확장을 논의하였으며, 이를 다변수인 경우로 확장하기 위해 Kronecker Product를 논의하였다.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제12B권1호
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• pp.31-36
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• 2002

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position; therefore, the position of rotor is an essential information. Although optical encoders or resolvers are used to provide the position information, these sensors are expensive. Moreover, in the high-speed region, switching angles are fluctuated back and forth out of the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. And the control algorithm to generate switching signals using a simple digital logic is presented. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.