• 전자공학회논문지A
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• 제30A권10호
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• pp.20-26
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• 1993

The base-collector capacitance of an npn bipolar transistor in bipolar or BiCMOS technology has significant influence on the switching performances, and comprises pnjunction component and MOS component. Both components have complicated dependences on the isolation oxide structure, epitaxial doping density, and bias voltage. Analytical/empirical formulas for both components are derived in this paper for a generic isolation structure as a function of epitaxial doping density and bias voltage based on some theoretical understanding and two-dimensional device simulations. These formulas are useful in estimating the effect of device isoation schemes on the switching speed of bipolar transistors.

• 한국데이터정보과학회:학술대회논문집
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• 한국데이터정보과학회 2005년도 추계학술대회
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• pp.161-169
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• 2005

In this paper we propose a fuzzy c-regression model based on weighted least squares support vector machine(LS-SVM), which can be used to detect outliers in the switching regression model while preserving simultaneous yielding the estimates of outputs together with a fuzzy c-partitions of data. It can be applied to the nonlinear regression which does not have an explicit form of the regression function. We illustrate the new algorithm with examples which indicate how it can be used to detect outliers and fit the mixed data to the nonlinear regression models.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1986년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 17-18 Oct. 1986
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• pp.601-606
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• 1986

In this paper, two methods of power circuit simulation is described in order to obtain the back data for design of current source inverter. One is steady-state analysis by differential equations during the various operating modes. Another method uses switching function, which represents the switching pattern of inverter, and direct-guadrature model of induction motor. The results of digital computer simulation by two methods are compared with the results of laboratory test.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1998년도 학술발표회논문집
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• pp.162-165
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• 1998

A certain degree of energy saving can be possible by controlling the delay time of occupancy sensor. In this paper a control circuit is designed for automatic control of delay time setting appropriate to different situations using a digital counter, two latches and an adder. The delay time is controlled by adjusting the time constant of RC circuit through on-off control of switching devices according to adder output, which determines the base current level of switching devices. And from PSpice simulation it is verified to function properly.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• 제어로봇시스템학회논문지
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• 제6권7호
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• pp.523-528
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• 2000

In this short note the characteristics of a nonlinear system of which the state trajectories are oscillating in the phase plane are overviewed. The physical concept of stuck and sliding patch phenomena are also introduced by adding some switching functions and their stability on the sliding patches are analyzed by using the Lyapunov stability theory and Frobenius theorem.

• 한국통신학회논문지
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• 제21권1호
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• pp.131-143
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• 1996

In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

• 한국의류학회지
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• 제37권4호
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• pp.526-539
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• 2013

This study analyzed the effects of internet fashion consumer's anticipated regret and the selection difficulty on decision making delay and purchase switching intention. The survey was conducted in 2012 on internet fashion consumers in their 20s to 40s from May 1 to June 30; subsequently, 487 responses were used for the data analysis. The anticipated regret of internet fashion consumers was composed of product, service, social psychology, and function-related anticipated regret. The selection difficulty of internet fashion consumers was composed of process, information, and experience-related selection difficulty. There are significant differences in anticipated regret, selection difficulty, decision making delay, and purchase switching intention by gender. The anticipated regret (product, service, and social psychology-related anticipated regret) and selection difficulty effected decision making delay. In addition, the anticipated regret for product and selection difficulty by process or information influenced purchase switching intention. The results of this study provide useful information on the success and efficient operation of internet shopping malls.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Journal of Semiconductor Engineering
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• 제3권2호
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.