• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.282-287
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• 2003

A network is made up of interconnected switching units. The role of a switching unit is to set up a connection between and input port and an output, according to the routing information. But then the most switching network use Banyan switch, their occurs the internal blocking , which attempts to use the same link two cells. This paper proposed and designed for a improvement Batch-Banyan network which can routed two path assignment between its input ports and output ports without only blocking. The network is constructed of two sorting blocks ($4{\times}4$), one switch network($8{\times}8$) block. As a result, the switch network performance increased 4% reduced to half of the hardware complexity of sorting boxes when compare the new switching system with Batcher-Banyan network system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6A
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• pp.558-564
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• 2007

3G Long Term Evolution, which aims for various mobile multimedia service provision by enhanced wireless interface, proposes VoIP-based voice service through a Packet Switching (PS) domain. As delay and loss-sensitive VoIP traffic flows through the PS domain, more challenging technical difficulties are expected than in Circuit Switching (CS) domain based VoIP services. Moreover, since 3G LTE, which adopts the OFDM as its physical layer, introduces Physical Resource Block (PRB) as a unit for transmission resources, new types of resource management schemes are needed. This paper proposes a PRB scheduling algorithm of MAC layer for VoIP service in 3G LTE and shows the simulation results. The proposed algorithm has two key parts; dynamic activation of VoIP priority mode to satisfy VoIP QoS requirements and adaptive adjustment of the priority mode duration in order to minimize the degradation of resource utilization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.66-76
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• 2009

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.793-794
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• 2011

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.2
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• pp.322-330
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• 1994

SIBs(Service Independent Building block) are defined in CCITT advanced intelligent network concept model for supporting various services in the future. This paper describes the protocol modeling and verification for basic call process SIB. For modeling, we use Petri Net and verify this modeling by analyzing reachability tree of Petri Net. Results of this paper should be used for design and implementation of basic call process SIB.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.163-165
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• 2016

AES-128 블록 암호에 대해 상관관계 전력분석 공격을 통해 비밀키를 추출할 수 있는 보안공격 시스템의 프로토타입을 개발했다. Verilog HDL로 모델링된 AES-128 암호 코어의 RTL 시뮬레이션을 통해 switching activity 정보를 추출하고, 이를 PowerArtist 툴을 이용하여 순시 전력을 도출하였다. 추출된 순시 전력으로부터 출력 레지스터의 hamming Weight 모델링과 상관관계 분석을 통해 128 비트의 비밀키 중 일부를 획득하는 보안공격 시스템을 개발하였다.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.1-9
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• 2022

Recently, a large number of cryptocurrencies and block chains have been continuously released. However, these cryptocurrencies and block chains are open to users without authorized verification and testing procedures, causing various reliability problems. Existing cryptocurrencies and blockchain test methods build a blockchain Testnet for a certain period of time by the developer without external verification by a third party, and after repeatedly self-testing and self-operating processes, commercialization is in progress by switching to the Mainnet. This self-verification method does not guarantee objectivity and publicness, and high reliability of customers cannot be realized. This study proposes a cryptocurrency and blockchain test interface and test control system as a third-party open test method.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.243-247
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• 2005

We propose an efficient block least-mean-square (BLMS) adaptive algorithm, in conjunction with error control coding, for direct-sequence code division multiple access (DS-CDMA) systems. The proposed adaptive receiver incorporates decision feedback detection and channel encoding in order to improve the performance of the standard LMS algorithm in convolutionally coded systems. The BLMS algorithm involves two modes of operation: (i) The training mode where an uncoded training sequence is used for initial filter tap-weights adaptation, and (ii) the decision-directed where the filter weights are adapted, using the BLMS algorithm, after decoding/encoding operation. It is shown that the proposed adaptive receiver structure is able to compensate for the signal-to­noise ratio (SNR) loss incurred due to the switching from uncoded training mode to coded decision-directed mode. Our results show that by using the proposed adaptive receiver (with decision feed­back block adaptation) one can achieve a much better performance than both the coded LMS with no decision feedback employed. The convergence behavior of the proposed BLMS receiver is simulated and compared to the standard LMS with and without channel coding. We also examine the steady-state bit-error rate (BER) performance of the proposed adaptive BLMS and standard LMS, both with convolutional coding, where we show that the former is more superior than the latter especially at large SNRs ($SNR\;\geq\;9\;dB$).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.611-614
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• 2012

Space-Time Block Code (STBC) is a simple transmit diversity scheme mitigating detrimental effects of fading channel. However, STBC receivers require channel knowledge and suffer from inaccurate channel estimation. Differential Space-Time Modulation (DSTM) renders the receiver a choice of coherent detection or non-coherent detection, depending on the availability of the channel information. Based on the simulated BER performances of these two schemes over various normalized Doppler frequency scenarios using LTE-like parameters, a benefit of adaptively switching the receiver type is investigated.