Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The Motion Estimator Implementation with Efficient Structure for Full Search Algorithm of Variable Block Size

다양한 블록 크기의 전역 탐색 알고리즘을 위한 효율적인 구조를 갖는 움직임 추정기 설계

  • 황종희 (연세대학교, 전기전자공학과) ;
  • 최윤식 (연세대학교, 전기전자공학과)
  • Published : 2009.11.25
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Abstract

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

움직임 추정은 영상 부호화 시스템에서 큰 비중을 차지하는 부분으로, 실시간 동작을 위해서는 효율적인 구조를 필요로 한다. 따라서 H.264 전체 시스템을 위한 움직임 추정기 블록의 구현은 부호화 과정을 고속으로 수행할 수 있도록 별도의 전용 하드웨어 모듈로 설계하는 것이 바람직하다. 본 논문에서는 많은 연산량을 효율적으로 줄일 수 있도록 병렬 처리를 바탕으로 움직임 추정 감지 블록, 41개의 SAD(Sum of Absolute Difference)값 계산 블록, 최소의 SAD값 계산과 움직임 벡터 생성 블록을 제안하고자 한다. 움직임 추정 감지 블록과 최소의 SAD값 계산기에서는 선계산(pre-computation) 방법을 적용함으로써, 입력 Switching Activity를 줄여 고속 구현이 가능하도록 하였으며, 움직임 추정 감지 블록과 41개의 SAD값 계산 블록에서 가장 많은 부분을 차지하는 가산기 구조를 일반적으로 사용되는 Ripple Carry Adder 대신에 Carry Skip Adder를 적용함으로써, Adder Tree 구조를 고속으로 처리할 수 있도록 하였다. 또한 외부에서 탐색 영역 제어와 같은 주요 변수를 쉽게 제어할 수 있도록 하여, 하드웨어 구조의 효율성을 높였다. 시뮬레이션 및 FPGA 검증 결과, 움직임 추정기의 임계 경로를 발생시키는 MED블록에서 일반적인 구조를 적용했을 때보다 19.89%의 Delay 감소 효과를 얻을 수 있었다.

Keywords

References

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