• Journal of KIISE:Computer Systems and Theory
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• v.26 no.6
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• pp.722-728
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• 1999

본 논문의 내용은 데이터 전송시 코드의 변화량을 줄여서 시스템이 소비하는 전략량을 감축하기 위한 효율적인 데이터 압축 알고리즘에 관한 것이다. 기존의 압축방법은 코드의 길이를 줄이는 것만을 목적으로 하였고 전송시 스위칭 동작량은 고려하지 않았다. 연속된 문자 코드의 서로 다른 비트 수를 해밍거리로 표시하는데 본 논문에서는 허프만 부호화 알고리즘에 의하여 발생된 압축률을 유지하면서 허프만코드를 재구성하여 스위칭 동작 횟수를 줄여 소비전력량을 줄이는 알고리즘을 제안한다. 실험결과 제안된 알고리즘은 아스키코드에 비하여 평균 15% , 허프만코드에 비하여 평균 4.6% 의 전력감축효과를 보였다.제안된 알고리즘은 압축률 개선에도 응용가능하다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 한국생물공학회:학술대회논문집
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• 2000.11a
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• pp.512-515
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• 2000

A parallel reactor system which is consisted of two trickle bed reactors (TBR) was developed for the biodegradation of trichloroethylene (TCE) in waste gas stream. The reactor were packed with porous ceramic materials and Burkholderia cepacia G4 was inoculated to form biofilms. Each reactor was operated alternatively in TCE degradation or reactivation mode, and the effect of switching time on TBR performance was investigated. The MO (monooxygenase) activity during the TCE transformation decreased below 10 % within 24 hr, but could be recovered to the initial high level within 10 hr after supplying the reactivation medium supplemented with phenol as a carbon source. This shows that the parallel TBR system has a great potential for the long-term stable treatment of TCE.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1153-1156
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• 2003

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques..

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.11-22
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• 1996

We address an issue of channel sharing among users by using a random assignment-transmitter-based (RA-T) spread-spectrum transmission scheme which permits the contention mode only in the transmission of a header while avoiding collision during the data packet transmission. Once the header being successfully received, the data packet is ready for reception by switching to one of programmable matched-filters. But the receoption may be blocked due to limited number of matched-filters so that this effect is taken into account in our analysis. For realistic analysis, we integrate detection performance at the physical level with channel activity at the link level through a markov chain model. We also consider an acknowledgement scheme to notify whether the header is correctly detcted and the data packet can be processed continuously, which aims at reducing the interference caused unwanted data transmission. It is shown that receiver complexity can be greatly reduced by choosing a proper number of RA codes at the cost of only a little throughput degradation.

• YAKHAK HOEJI
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• v.34 no.5
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• pp.334-340
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• 1990

The bioequivalence of Mandol and Mancef (cefamondole nafate injection preparation) was investigated for 8 healthy human volunteers. Cefamandole nafate hydrolysis to cefamandole base in the blood and shows antibacterial activity. As the rate of the hydrolysis can be varied according to the buffer used in the preparation, the bioequivalence of cefamandole nafate I.V. was studied. A new HPLC method, the column switching technique, was developed and used for the simultaneous determination of cefamandole and cefamandole nafate in the plasma and in the urine. There were no statistically significant difference in between Mandol and Mancef for the parameters of AUC and Cp 0.25 hr even through the power of the test was not enough.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.79-86
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• 2002

This paper presents a low power scheduling and allocation algorithm for multiple supply voltage. The proposed supply voltage scheduling algorithm determines the control step to execute a possible the operation experimentally using another supply voltage level. Also, the switching activity using component library. and the supply voltage allocation method uses the graph coloring technique for low power, the proposed algorithm Proves the effect through various high level benchmark examples to adopt a multiple supply voltage scheduling algorithm for low power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.463-469
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• 2016

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.