• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.842-844
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• 2004

The Back Up Breaker and Making Switch are very important equipments for the short circuit test facility, and contacts are the most important parts of the above switches. There are very many kind of contacts according to switches characteristic and should be done the verification test before use, especially development contacts. This study describes the class of switches, arc chute, material of whole contacts and essential test for verification. The essential test for verification are dielectric test, mechanical operation test, short-time withstand current test, load current breaking test, and short-circuit making current test etc.

• Journal of Power Electronics
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• 제12권5호
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• pp.723-730
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• 2012

This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

• Journal of Power Electronics
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• 제12권6호
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• pp.859-868
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• 2012

In this paper, a novel bidirectional DC-DC converter employing soft switching technique was proposed. Compare to conventional bidirectional converters, the main switches of proposed converter are operated without switching losses. Moreover, auxiliary switches are used, and the switches are operated under zero voltage switching (ZVS) and zero current switching (ZCS) condition. To verify the validity of the proposed converter, mode analysis, design procedure, simulation and experimental results are presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.686-688
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• 1996

Network reconfiguration is performed by opening/closing two types of switches, tie and sectionalizing switches. A whole feeder, or part of a feeder, may be served from another feeder by closing a tie switch linking the two while an appropriate sectionalizing switch must be opened to maintain radial structures. In loss reduction, the problem is to identify tie and sectionalizing switches that should be closed and opened, respectively, to achieve a maximum loss reduction. In this paper, it is introduced to propose the reconfiguration plan for loss reduction by using the Civanlar's loss reduction formular.

• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.13-17
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• 2005

The link e daggregation between 10GbE switches requires an advanced framistribution method to be properly and efficiently applied. The fixed or dynamic frame distribution methods, formerly proposed, cannot fully utilize the aggregated links, where the receiving terminal only attaches to a pre-specified link among multiple physical links. A frame distribution method using padding is proposed for the link aggregation between 10GbE switches to solve this problem. We compared the performance of the proposed method with those of the static and dynamic frame distribution methods. As a result, the proposed method shows a better performance when the offered load is below 0.7 and the average length of the frames is longer than 954 bytes.

• Journal of Power Electronics
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• 제15권4호
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.15-16
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• 2012

This paper is study on a novel high efficiency step up-down converter using loss-less snubber capacitor. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.74-76
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• 2019

This paper proposes an open-switch fault tolerant strategy based on the model predictive control for a full bidirectional switches indirect matrix converter (FBS-IMC). Compared to the conventional Indirect Matrix Converter (IMC), the FBS-IMC can provide healthy current path when open-switch fault is occurred. To keep the continuous operation, the fault tolerant strategy is developed by means of reversing the DC-link voltage polarity regardless of the faulty switch location in the rectifier or inverter stage. Therefore, the proposed control strategy can maintain the same input and output performances during the faulty condition as the normal condition. The simulation results are given to verify the effectiveness of the proposed strategy.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권2호
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• pp.733-750
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• 2019

Software Defined Networking (SDN) is a new network paradigm, allowing administrators to manage networks through central controllers by separating control plane from data plane. So, one or more controllers must locate outside switches. However, this separation may cause delay problems between controllers and switches. In this paper, we therefore propose a Priority-based Scheduling policy for OpenFlow (PSO) to reduce the delay of some significant traffic. Our PSO is based on packet prioritization mechanisms in both OpenFlow switches and controllers. In addition, we have prototyped and experimented on PSO using a network simulator (ns-3). From the experimental results, PSO has demonstrated low delay for targeted traffic in the out-of-brand control network. The targeted traffic can acquire forwarding rules with lower delay under network congestion in control links (with normalized load > 0.8), comparing to traditional OpenFlow. Furthermore, PSO is helpful in the in-band control network to prioritize OpenFlow messages over data packets.

• 한국정보과학회논문지:정보통신
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• 제34권3호
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• pp.203-217
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• 2007

본 논문은 출력 버퍼를 장착한 크로스바 스위치로 구성된 다양한 네트워크들의 성능 예측 모형을 제안하고, 스위치에 장착된 버퍼의 개수 증가에 따른 성능 향상 추이를 분석하였다. 스위치 내부에 버퍼를 장착하는 기법은 네트워크 내부의 데이타 충돌 문제를 효과적으로 해결하고, 네트워크 성능 및 신뢰도를 높이는 방법으로 널리 알려져 있다. 또한, 크로스바 스위치를 이용하여 네트워크를 구성할 경우 네트워크 내부의 스위치들 간의 연결 형태 그리고, 각 스위치 내부의 데이타 이동 패턴에 따라 네트워크 특성이 결정된다. 본 논문에서는 크로스바 스위치로 구성된 세 가지 서로 다른 형태의 네트워크 : 다단 연결 망(MIN), Fat-tree 망, 그리고 일반 통신망 등의 성능 분석모형을 제안하였다. 제안한 분석 모형은 네트워크 내부 스위치에 장착된 버퍼의 개수와 무관하게 네트워크 성능 평가의 두 가지 주요 요소인 네트워크 정상상태 처리율(Normalized Throughput, NT)과 네트워크 지연시간을 예측한다. 제안한 수학적 성능 분석 연구의 실효성을 검증하기 위하여 병행된 시abf레이션 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이타와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다. 또한 분석 결과 네트워크 내부 스위치에 많은 버퍼를 장착 할수록 상대적으로 정상상태 처리율의 증가율은 감소하고, 네트워크 지연시간은 증가하는 것으로 나타났다.