• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.261-267
• /
• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• ETRI Journal
• /
• v.33 no.1
• /
• pp.136-139
• /
• 2011

A modular upgrade design for packet transport switch nodes is presented where packet loss is dramatically reduced by intra-module and inter-module buffer sharing. This modular design offers significant cost and power reduction in a high-data-rate system where buffers are highly costly and power-greedy.

• Proceedings of the IEEK Conference
• /
• 2001.06a
• /
• pp.281-284
• /
• 2001

In this paper, we design the Sorting-Banyan network with an efficient buffer and sorting management schema that makes switch be capable of supporting delay sensitive as well as loss sensitive. The proposed switching network is remodeled that based on Batcher-banyan network that have eight input and output ports The structure of designed switching network is constructed of modified banyan network with 2-way routing paths and two plane sorting networks. we have analysed the maximum throughput of the switch, under the uniform random traffic load, the FIFO discipline has increased by about 11% when we compare the switching system with the input buffering system.

• Proceedings of the Korea Society for Simulation Conference
• /
• 1999.04a
• /
• pp.1-5
• /
• 1999

An ATM switch is the basic component of an ATM network, and its functioning is to switch incoming cells arriving at an input port to the output port associated with an appropriate virtual path. In case of an ATM switch with buffer sharing scheme, the performance analysis is very difficult due to the interactions between the address queues. In this paper, the influences of the degree of traffic burstiness and some traffic routing properties are investigated by using the simulation. Also, some cell access strategies including priority access and cell dropping are compared in terms of cell loss probability.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.4
• /
• pp.1246-1264
• /
• 2000

An input-output buffering switch operates in either of tow different cell loss modes; Backpressure mode and Queueloss mode. In the previous studies, the Backpressrue mode is more effective at low traffic loads, and the Queueloss mode performs better at high traffic. We propose a new operation mode, called Hybrid mode, which adopts the advantages of he Backpressure and the Queueloss mode. Backpressure and Queueloss modes are distinguished from whether a cell loss occurs at the output buffer or not when output buffer overflows, irrespective of input buffer status. In order to simply combine Backpressure and Queueloss mode, the change of input traffic load must be measured. However, in the Hybrid mode, simply both of the input and output buffer overflow and checked out to determine the cell discard. The performance of the Hybrid mode is compared with those of the Backpressure and the Queueloss mode under random and bursty traffic. This paper show that the Hybrid mode always gives the best performance results for most ranges of load values.

• Journal of KIISE:Information Networking
• /
• v.29 no.6
• /
• pp.738-748
• /
• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.782-787
• /
• 2000

The monolithic single-pole three-throw(SP3T) GaAs PIN diode switch circuit for the broadband and high power application was designed, fabricated and characterized. To improve the power handling capability, buffer layers of the diode employ both low temperature buffer and superlattice buffer. The diode show the breakdown voltage of 65V and turn-on voltage of 1.3V. The monolithic integrated switch employed microstrip lines and backside via holes for low-inductance signal grounding. The vertical epitaxial PIN structure demonstrated better microwave performance than planar type structures due to lower parasitics and higher quality intrinsic region. As the large signal characteristics of the fabricated SP3T MMIC switch, the insertion loss was measured less than 0.6dB and the isolation better than 50dB when the input power was increased from 8dBM to 32dBm at 14.5GHz.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 1992.04b
• /
• pp.261-261
• /
• 1992

• Progress in Superconductivity
• /
• v.5 no.1
• /
• pp.13-16
• /
• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.855-869
• /
• 1997

In this paper, we proposed two kids of dynamic priority control mechanisms controlling the cell service ratio in order to improve the QOS(Quality of Service). We also analyse theoretically the characteristics of cell loss probability and mean cell delay time by applying the proposed priority control mechanisms to ATM switch with output buffer. The proposed priority control mechanisms have the same principles of storing cells into buffer but the different principles of serving cells from buffer. The one is the control mechanism controlling the cell service ratio according to the relative cell occupancy ratio of buffer, the other is the control mechanism controlling the cell service ratio according to both the relative cell occupancy ratio of buffer and the average arrival rate. The two service classes of our concern are the delay sensitive class and the loss sensitive class. The analytical results show that the proposed control mechanisms are able to improve the QOS, the characteristics of cell loss probability and mean cell delay time, by selecting properly the relative cell occupancy ratio of buffer and the average arrival rate. conventional DLB algorithm does not support synchronous cells, but the proposed algorithm gives higher priority to synchronous cells. To reduce synchronous cell loss rate, the synchronous cell detector is used in the proposed algorithm. Synchronous cell detector detects synchronous cells, and passes them cells to the 2nd Leaky-Bucket. So it is similar to give higher priority to synchronous cells. In this paper, the proposed algorithm used audio/video traffic modeled by On/Off and Two-state MMPP, and simulated by SLAM II package. As simulation results, the proposed algorithm gets lower synchronous cell loss rate than the conventional DLB algorithms. The improved DLB algorithm for multimedia synchronization can be extended to any other cells which require higher priority.