• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.1
• /
• pp.80-90
• /
• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Journal of KIISE:Information Networking
• /
• v.34 no.3
• /
• pp.193-202
• /
• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of Internet Computing and Services
• /
• v.7 no.6
• /
• pp.113-121
• /
• 2006

To reduce switch cost, the optimum numbers of tunable wavelength converters (TWCs) and internal wavelengths required for contention resolution of asynchronous and variable length packets like internet traffics, is presented in the optical packet switch (OPS) with the shared fiber delay line (FDL) buffer. To optimize TWCs and internal wavelength related to on OPS design cost, we proposed a scheduling algorithm for the limited TWCs and internal wavelengths. For three TWC alternatives (not shared, partially shared, and fully shared cases), the optimum numbers of TWCs and internal wavelengths to guarantee minimum pocket loss are evaluated to prevent resource waste. Under o given load, TWCs and internal wavelengths could be significantly reduced, guaranteeing the same pocket loss probability as the performance of on OPS with full TWCs and internal wavelengths.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.8B
• /
• pp.812-821
• /
• 2009

This paper proposes a novel dynamically reconfigurable switch for various multimedia applications in hybrid NoC systems. Current NoC systems, which adopt hybrid NoC structure with fixed switch and job distribution algorithms, require designers to precisely predict the property of applications to be processed. This paper proposes a reconfigurable switch which minimizes buffer overflow in various multimedia applications running on an NoC system. To verify the performance of the proposed system, we performed experiments on various multimedia applications running on embedded systems, such as MPEG4 and MP3 decoder, GPS positioning system, and OFDM demodulator. Experimental results show that buffer overflow has been decreased by 41.8% and 29.0%, respectively, when compared with NoC systems having sub-clusters with mesh or star topology. Power usage has been increased by 2.3% compared with hybrid NoC systems using fixed switches, and chip area has been increased from -0.6% to 5.7% depending on sub-cluster topology.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.5 no.5
• /
• pp.429-432
• /
• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• Journal of Communications and Networks
• /
• v.1 no.3
• /
• pp.145-152
• /
• 1999

A new switch architecture is presented to enhance out-put queuing in photonic packet switches. Its appkication is for a packet switching enviroment based on the optical transport of fixed length packets. This architecture consists of a couple of cas-cading switching elements with output queuing, whose buffer ca-pacity is limited by photonic technology. The introduction of a suitable buffer management allows a very good and balanced ex-ploitation of the available optical memories, realized with fiber de-lay lines. In particular, packet loss performance is here evaluated showing the improvement with respect to the single switch and a way to design large optical switches is shown in order to meet broadband network requirements.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.133-136
• /
• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.36T no.4
• /
• pp.82-87
• /
• 1999

The Asynchronous Transfer Mode(ATM) networks are being adopted as backbones over various parts of Internet. TCP is one of the most widespread transport protocols and can be used with ATM. But, TCP shows poor end-to-end performance on ATM networks. Effective throughput of TCP over ATM can be quite low when cells are dropped at the congested ATM switch. As congested link transmits cells from corrupted packets, it wastes bandwidth and throughput becomes low. This paper examines the behavior of TCP over ATM-UBR using EPD switch in a broadband environment. As threshold value closes to the buffer size, the buffer can be used more efficiently, but more drops and retransmission occur. If the threshold value is much less than buffer size, efficiency becomes low, but few drops can be happen. Therefore, the decision of threshold value becomes important factor.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.4
• /
• pp.947-960
• /
• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.5
• /
• pp.1037-1050
• /
• 2000

A goal of a BISDN network is to provided integrated transport for a wide range of applications such as teleconferencing, Video On Demand etc. There require multipoint communications in addition to conventional point-to-point connections. Therefore multicast capabilities are very essential in multimedia communications. In this paper, we propose a new multicast cell scheduling method on the Parallel Multicast Packet Switch with Ring network: PMRN which are based on separated HOL. In this method, we place two different HOLs, one for unicast cells and the other for multicast cells. Then using non-FIFO scheduling, we can schedule both unicast cells and multicast cells which are available at the time in the input buffer. The simulation result shows that this method reduces the delay in the input buffer and increases the efficiency of both point-to-point network and ring network and finally enhances the bandwidth of the overall packet switch. A goal of a BISDN network is to provided integrated transport for a wide range of applications such as teleconferencing, Video On Demand etc. There require multipoint communications in addition to conventional point-to-point connections. Therefore multicast capabilities are very essential in multimedia communications. In this paper, we propose a new multicast cell scheduling method on the Parallel Multicast Packet Switch with Ring network: PMRN which are based on separated HOL. In this method, we place two different HOLs, one for unicast cells and the other for multicast cells. Then using non-FIFO scheduling, we can schedule both unicast cells and multicast cells which are available at the time in the input buffer. The simulation result shows that this method reduces the delay in the input buffer and increases the efficiency of both point-to-point network and ring network and finally enhances the bandwidth of the overall packet switch.