• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.312-315
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• 1995

The base/gate drive suppression method proposed by Joshi and Bose is that which detects the output current polarity of the leg and, according to the polarity, suppresses the base/gate drive of one of the ore switching devices of the leg. This method has the merit that it does not have the conventional dead time problem, reduces the power loss of the driving circuit and others. But this method has difficulty in implementation. In this paper, a new base/gate drive suppression method by detecting not the output current polarity but the output voltage polarity is proposed. The proposed method is easier to implement than Joshi and Bose's method.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• 한국항공운항학회:학술대회논문집
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• 2007.06a
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• pp.121-124
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• 2007

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.186-190
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• 2000

This paper propose a "Active common-mode voltage damper circuit" that capable of a suppression of a common-mode voltage produced in the PWM VSI. The four level half-bridge PWM inverter circuit and common-mode transformer are incorporated into the "Active common-mode voltage damper" the design method of which is presented Effect of "Active common-mode voltage damper" in this paper verifies a propriety and effectiveness in 2.2[kW] induction motor drive using IGBT inverter. Experimental results show that "common-mode voltage damper" makes contributions to reducing a high frequency leakage current and common-mode voltage.leakage current and common-mode voltage.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.240-242
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• 1993

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1053-1056
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• 2003

A distortion suppression technology for employing multiple inputs in 3n+1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of inputs in current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to sum of parasitic capacitance in input terminals, to the derivative of the output signal and also to the inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.2
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• pp.222-227
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• 1995

A new IGBT structure, which may suppress latch-up phenomena considerably, is proposed and verified by MEDICI simulation. The proposed structure employing the segmented $n^{+}$ buffer layer increases latch-up current capability due to suppression of the current flowing through the resistance of $p^{-}$ well, $R_{p}$, which is the main cause of latch-up phenomena without degradation of forward characteristics. The length of the $n^{+}$ buffer layer is investigated by considering the trade-off between the latch-up current capability and the forward voltage drop. The segmented $N^{+}$ buffer layer results in better latch-up immunity in comparison with the uniform buffer layer.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.74-75
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• 2017

This paper proposes a control scheme of the voltage ripple suppression for the permanent magnet exciter generator. The output voltage of the permanent magnet excitation generator is affected by the field current, load current and the engine speed. The engine speed can be controlled by the governor. But, the actual frequency is changed at the starting and a sudden load variation. As a result, output voltage overshoot and undershoot can decrease the power quality in the grid system. The proposed control scheme uses a frequency factor to control the field current of the generator for the voltage ripple reduction. Because of the linkage flux is proportional to the frequency, the instantaneous frequency can consider the linkage flux. The proposed control method shows the improved control performance for the permanent magnet excitation generator through simulation.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.293-296
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• 2005

This paper is concerned with the sweeping damping controller for beam. The active damping characteristics can be enhanced by moving the damper along the longitudinal axis. In this paper, the equation of motion for a beam including a sweeping damping controller is derived and its stability is proved by using Lyapunov stability theorem. It is found from the theoretical study that the sweeping damping controller can enhance the active damping characteristics, so that a single damper can suppress all the vibration modes of the beam. To demonstrate the concept of the sweeping damping control, the eddy current damper was applied to a cantilever, where the eddy current damping can move along the axis. The experimental result shows that the sweeping eddy current damper Is an effective device for vibration suppression.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1349-1362
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• 2017

In order to further improve the harmonic suppression capability of conventional 12-pulse rectifiers, this paper proposes a low harmonic 12-pulse rectifier using an Active Inter-Phase Reactor (AIPR). Through a detailed analysis of the relationship between the input current, output current and circulating current of the DC side, the mechanism where the AC grid side current harmonics can be suppressed by the DC side circulating current is revealed. On this basis, an interleaved APFC controlled by a DSP is designed and used as an AIPR along with an interphase reactor. A simulation is carried out with MATLAB/Simulink and an experiment is performed on a 9-kVA prototype. The obtained results verify the feasibility and validity of the proposed approach. Compared with a traditional 12-pulse rectifier, the THD can be reduced to 1/5 of the original value, and the capacity of the AIPR is only 2% of the load power. Thus, it is suitable for high-power applications.