• 한국컴퓨터산업학회논문지
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• 제4권12호
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• pp.1043-1052
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• 2003

본 논문에서는 비디오코딩의 움직임 추정을 위한 빠른 움직임 추정알고리즘을 제안하였다. 제안된 알고리즘은 다단계 연속제거 알고리즘과 효율적인 다단계 연속제거 알고리즘에 기초하고 있다. 제안된 알고리즘은 계층적으로 탐색점을 추출하여 매우 많은 연산량을 필요로 하는 정합 연산량을 감소시키면서 최상의 움직임벡터를 얻을 수 있다. 실험을 통하여 제안된 알고리즘의 효율성을 확인하였다.

• Communications for Statistical Applications and Methods
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• 제26권2호
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• pp.175-189
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• 2019

The problem of the estimation of quantitative sensitive variable using the item sum technique (IST) on successive occasions has been discussed. IST difference, IST regression, and IST general class of estimators have been proposed to estimate quantitative sensitive variable at the current occasion in two occasion successive sampling. The proposed new estimators have been elaborated under Trappmann et al. (Journal of Survey Statistics and Methodology, 2, 58-77, 2014) as well as Perri et al. (Biometrical Journal, 60, 155-173, 2018) allocation designs to allocate long list and short list samples of IST. The properties of all proposed estimators have been derived including optimum replacement policy. The proposed estimators have been mutually compared under the above mentioned allocation designs. The comparison has also been conducted with a direct method. Numerical applications through empirical as well as simplistic simulation has been used to show how the illustrated IST on successive occasions may venture in practical situations.

• Communications for Statistical Applications and Methods
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• 제24권3호
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• pp.255-269
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• 2017

This article explores the analysis of longitudinal surveys in which same units are investigated on several occasions. Multivariate exponential ratio type estimator has been proposed for the estimation of the finite population median at the current occasion in two occasion longitudinal surveys. Information on several additional auxiliary variables, which are stable over time and readily available on both the occasions, has been utilized. Properties of the proposed multivariate estimator, including the optimum replacement strategy, are presented. The proposed multivariate estimator is compared with the sample median estimator when there is no matching from a previous occasion and with the exponential ratio type estimator in successive sampling when information is available on only one additional auxiliary variable. The merits of the proposed estimator are justified by empirical interpretations and validated by a simulation study with the help of some natural populations.

• 전기학회논문지
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• 제68권1호
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• 응용통계연구
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• 제27권4호
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• pp.513-521
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• 2014

일반적으로 현 시점에서 목표로 하고 있는 추정량의 산포가 지난시점의 추정량의 산포보다 크다면 지난시점과 비교하여 현 시점의 표본의 크기는 줄어드는 것이 타당하다. 계속조사에서 지난 시점의 추정량의 변동계수와 모집단의 크기 변동과 현 시점의 추정량의 목표오차를 이용하여 표본의 크기를 결정하는 것을 연구한 여러 논문들이 있다. 그런데 모집단은 크기의 변동과 산포의 변동이 있을 수 있으므로 본 연구에서는 지난 시점의 추정량의 변동계수와 모집단의 크기, 모집단의 산포 변동과 현 시점의 추정량의 목표오차를 반영하여 현 시점의 표본의 크기를 구하는 문제를 연구한다. 또한 모의실험을 통하여 기존 표본크기의 공식들과 비교분석한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• 한국수산과학회지
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• 제26권4호
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• pp.369-379
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• 1993

1992년 동계에 췌셰픽만의 꽃게자원에 대하여 예망을 사용한 연속채집법에 의한 어획 효율성을 조사하였다. 일반선형모델 분석에 따르면 26회에 걸친 야외시험 결과 어획효율성은 저질이나 수심, 사용된 조사선박에 따라 통게학적으로 유의한 차이가 나타나지 않았다. 예망효율(즉, 어획율)은 Leslies방법과 단순히 개조된 방법 등의 두 방법을 사용하여 추정하였다. 평균 어획율은 0.26 (표준오차:0.03)으로 추정되었는데 이는 한번의 예망을 사용하여 채집장소에 존재하고 있는 꽃게 가운데 단지 $26\%$($95\%$ 신뢰한계 : $20{\sim}32\%$)를 잡을 수 있다는 의미이다. 예망효율은 꽃게의 밀도가 증가함에 따라 지수적으로 감소하였다.

• Structural Engineering and Mechanics
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• 제82권2호
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• pp.245-258
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• 2022

Many Structural Health Monitoring (SHM) methods have been proposed for structural damage diagnosis and prognosis. However, SHM for pinched hysteretic structures can be problematic due to the high level of nonlinearity. The model-free hysteresis loop analysis (HLA) has displayed notable robustness and accuracy in identifying damage for full-scaled and scaled test buildings. In this paper, the performance of HLA is compared with seven other SHM methods in identifying lateral elastic stiffness for a six-story numerical building with highly nonlinear pinching behavior. Two successive earthquakes are employed to compare the accuracy and consistency of methods within and between events. Robustness is assessed across sampling rates 50-1000 Hz in noise-free condition and then assessed with 10% root mean square (RMS) noise added to responses at 250 Hz sampling rate. Results confirm HLA is the most robust method to sampling rate and noise. HLA preserves high accuracy even when the sampling rate drops to 50 Hz, where the performance of other methods deteriorates considerably. In noisy conditions, the maximum absolute estimation error is less than 4% for HLA. The overall results show HLA has high robustness and accuracy for an extremely nonlinear, but realistic case compared to a range of leading and recent model-based and model-free methods.

• 전기전자학회논문지
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• 제14권1호
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• pp.8-16
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• 2010

본 논문에서는 CCD 이미지 처리를 위한 최대 15MS/s의 속도의 중저속 아날로그-프론트 엔드(analog-front end, AFE)에서 사용될 수 있는 연속근사 ADC(Successive Approximation ADC, SA-ADC)의 설계를 제안한다. 파이프라인 ADC와 달리 SA-ADC는 동작주파수의 변화에 따른 전력소모의 스케일링(scaling) 효과가 크므로 저속에서 중속에 이르는 넓은 범위의 가변 데이터 처리 속도의 응용에 매우 효과적이다. 제안하는 설계는 입력 신호의 샘플링 동작을 내부 DAC(sub-DAC)로부터 따로 분리한 후, 커패시터 커플링을 통해 차동 결합함으로써 신호경로에 이르는 부하를 크게 줄이는 "차동 커패시터 커플링 기법"의 도입, 연속근사의 기법적 측면에서 signed 구조를 활용하여 데이터 변환주기 이전에 홀드된 입력신호로부터 미리 MSB(sign bit)를 결정함으로써 1사이클의 변환주기를 절약하고 내부 DAC의 하드웨어를 1비트 줄이는 구조와 같은 특징을 갖고 있다. 본 설계는 3.3V $0.35{\mu}m$ CMOS 공정으로써 설계하고 Spectre 시뮬레이션을 이용하여 그 특성을 분석함으로써 CCD 아날로그 프론트-엔드에 적용될 수 있음을 입증하였다.