• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.63-68
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• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.04a
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• pp.166-171
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• 2004

In this study, shape optimization of micro-static mixer with a cantilever beam was accomplished for mixing the mixing efficiency by using successive response surface approximations. Variables were chosen as the length of cantilever beam and the angle between horizontal and the cantilever beam. Sequential approximate optimization method was used to deal with both highly nonlinear and non-smooth characteristics of flow field in a micro-static mixer. Shape optimization problem of a micro-static mixer can be divided into a series of simple subproblems. Approximation to solve the subproblems was performed by response surface approximation, which does not require the sensitivity analysis. To verify the reliability of approximated objective function and the accuracy of it, ANOVA analysis and variables selection method were implemented, respectively. It was verified that successive response surface approximation worked very well and the mixing efficiency was improved very much comparing with the initial shape of a micro-static mixer.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.386-391
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• 2003

This paper focuses on robust $H_{\infty}$ control for bilinear systems with time-varying parameter uncertainties and exogenous disturbance via output feedback. $H_{\infty}$ control is achieved via separation into a $H_{\infty}$ state feedback control problem and a $H_{\infty}$ state estimation problem. The suitable robust stabilizing output feedback control law can be constructed in term of approximated solution to x-dependent Riccati equation using successive approximation technique. Also, the $H_{\infty}$ filter gain can be constructed in term of solution to algebraic Riccati equation. The output feedback control robustly stabilizes the plant and guarantees a robust $H_{\infty}$ performance for the closed-loop systems in the face of parameter uncertainties and exogenous disturbance.

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.171-177
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• 2003

In this paper, we investigate a robust $H_{\infty}$ state feedback control technique for continuous time bilinear systems with an additive disturbance input. The nonlinear robust $H_{\infty}$control for bilinear systems requires a solution to the state dependent algebraic Riccati equation (SDARE). We present a new robust $H_{\infty}$control technique based on the successive approximation method for solving the SDARE by converting bilinear systems into time-varying linear systems. The proposed control method guarantees robust stability for closed loop bilinear systems. The proposed algorithm is verified by numerical examples.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.481-482
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• 2007

This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.1996-1998
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• 2001

This paper presents the closed-loop composite control for weakly coupled bilinear systems with a quadratic performance criterion. The Riccati equation for weakly coupled bilinear system is decomposed into three reduced Riccati equations by the weak coupling theory, and we obtain optimal solutions of each reduced Riccati equation using successive Galerkin approximation(SGA). We design the composite control law that consists of optimal solutions of each reduced Riccati equation. The proposed algorithm reduces the disadvantages of SGA method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

• Journal of Applied and Pure Mathematics
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• v.4 no.5_6
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• pp.233-247
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• 2022

This manuscript addressed, the existence and uniqueness result for random impulsive stochastic functional differential equations with finite time delays. The study of random impulsive stochastic system is a new area of research. We interpret the meaning of a stochastic derivative and how it differs from the classical derivative. We prove the existence and uniqueness of mild solutions to the equations by using the successive approximation method. We conclude the article with some interesting future extension. This work extends the work of [18, 12, 20]. Finally, an example is given to illustrate the theoretical result.