• Journal of Korean Society of Steel Construction
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• v.26 no.5
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• pp.407-418
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• 2014

As a continuing work of previously conducted standard tension tests, full-scale flexural tests were conducted in this study to assess the structural performance the CJP groove welded joints connecting thick HSA800 plates. Two welding electrodes were available at the time of this experimental research; one was GMAW-based electrode A and the other FCAW-based electrode B. Three full-scale box-type beam specimens with single bevel- and V-groove CJP welded joints were fabricated from 60mm and 25mm thick HSA800 plates according to the AWS-prequalified groove welded joint details. In designing the specimens, all possible limit states like local and lateral torsional buckling were carefully controlled in order to induce flexural plastic yielding or eventual joint fracture. All the CJP joints made by both welding electrodes showed satisfactory performance and were able to transfer the tensile flange forces higher than that corresponding to the measured tensile strength of HSA800 flange plates. However, it should be noted that, during fabrication, serious concerns about the welding efficiency and workability of the GMAW-based electrode were raised by a certified welder. The fracture occurred at the unbeveled (or vertical) interface between the weldment and the base metal when the GMAW-based electrode was used in the single-bevel joint, implying the possibility of insufficient melting. Thus, the FCAW-based electrode B is again recommended as the choice of welding electrode for HSA800 plates. The limited test data of this study implies that the V-groove CJP joint should be used in favor of the single bevel CJP joint, if possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of the Korea Institute of Building Construction
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• v.16 no.3
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• pp.237-245
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• 2016

Structural performance and durability of ultra high performance concrete could demonstrate optimal performance when unity was kept. Accordingly, it is necessary to involve the characteristics and quantitative surface treatment at the same time in order to retain oneness of Ultra-High-Performance Concrete(UHPC) according to construction joint occurrence. Therefore, this study derives a reasonable surface treatment method in a material's point of view through the shear adhesion performance evaluation according to the construction joints surface processing method as a part for securing the adhesion performance of the construction joints when casting UHPC. 180 MPa of required average strength was used for mix of UHPC and surface treatment method was set to totally 7 level that MN, GR-10-0, GR-20-0, GR-30-0, SH-30-5, SH-30-10. After the specimen were manufactured to a size of $150{\times}150{\times}150mm$, Direct shear test was performed to evaluate the shear adhesion strength. As a result, it was confirmed that the adhesion performance was improved when executing a surface treatment for the construction joint interface and standard of failure mode of specimen was over Type C. Also, It was considered that interface of cross section and depth of concavo-convex should be concerned.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.437-444
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• 2014

The integrated modular avionics (IMA) system has quite a number of line repalceable moduels (LRMs) in a cabinet. The LRM performs functions like line replaceable units (LRUs) in federated architecture. The video processing module (VPM) acts as a video bus bridge and gateway of ARINC 818 avionics digital video bus (ADVB). The VPM is a LRM in IMA core system. The ARINC 818 video interface and protocol standard was developed for high-bandwidth, low-latency and uncompressed digital video transmission. FPGAs of the VPM include video processing function such as ARINC 818 to DVI, DVI to ARINC 818 convertor, video decoder and overlay. In this paper we explain how to implement VPM's Hardware. Also we show the verification results about VPM functions and IP core performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.279-286
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• 2010

RFID reader protocol is an interface between RFID readers and higher (host) such as RFID middlewares and applications. At present, reader protocols provided by vendors are different from each other and there are compatibility problems in environment using heterogeneous readers. In this paper, to solve this problem, an RFID reader which supports LLRP(Low Level Reader Protocol), a well-known standard reader protocol presented by EPCglobal is designed and implemented. It is designed with two modules and supports various interfaces for easy adaptation to various applications. The LLRP protocol is implemented over a embedded LINUX multi-thread environment. It not only supports almost all properties of LLRP, and is designed with flexible hardware/software architecture to meet various requirements.

• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.5
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• pp.418-428
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• 2016

In this study, a Vessel Shore Report Management System (VSRMS) is developed for the International Maritime Organization (IMO), Maritime Service Portfolio (MSP) Number 8, which comprises vessel shore reporting. Several documents have to be completed before the arrival/departure of a vessel at a port, as each national port has its own reporting format and data. The present vessel reporting system is inefficient, time-consuming, and involves excessive paperwork, which results in duplications and errors. To solve this problem, in this study, the vessel reporting formats and data contents of various national ports are investigated, as at present, the reporting documents required by the current IMO standard includes insufficient information which is requested by national ports. Initially, the vessel reporting information of various national ports are collected and analyzed. Subsequently, a database structure for managing vessel reporting data for ports worldwide is devised. To make the transfer of data and the exchange of information of vessel reports much more reliable, efficient, and paper-free, VSRMS, which is a software application for the simplification and facilitation of vessel report formalities, is developed. This application is developed using the latest Microsoft C#.Net Programming Language in the Microsoft Visual Studio framework 4.5. It provides a user interface and a backend MySQL server used for database management. SAP Crystal Reports 2013 is used for designing and generating vessel reports in the original report formats. The VSRMS can facilitate vessel reporting and improve data accuracy through the reduction of input data, efficient data exchange, and reduction of the cost of communication. Adoption of the VSRMS will allow the vessel shore reporting system to be automated, resulting in enhanced work efficiency for shipping companies. Based on this information system and architecture, the consensus of various international organizations, such as the IMO, the International Association of Marine Aids to Navigation and Lighthouse Authorities (IALA), the Federation of National Associations of Ship Brokers and Agents (FONASBA), and the Baltic and International Maritime Council (BIMCO), is required so that vessel reporting is standardized internationally.

• The Journal of Korean Association of Computer Education
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• v.4 no.1
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• pp.43-52
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• 2001

The aim of this paper is to develop a network-based collaborative learning system based on cooperative learning, computer simulation, role playing, and web-based instruction, which is called NetClass. It is an educational system of hybrid-type, and supports three learning modes as a distributed network, a stand-alone system, or a web browser. To accomplish the purpose of this paper, we have studied on the following topics. First, we selected appropriate learning contents among dilemmas on information ethics. Second, a Collaborative Dilemma-solving Learning Model (CDLM) was designed, and this model means systematic procedures that leaners can notice others' feeling and thinking and predict the results of his actions by introducing interactions among learners on computer networks. Third, Collaborative Learning System Model based on standard architecture of an educational system was proposed. Fourth, we developed many components such as network components, database components, and interface components.

• Journal of the Korea Society for Simulation
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• v.17 no.1
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• pp.43-52
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• 2008

The High Level Architecture(HLA) is the IEEE 1516 standard for interoperation between heterogeneous simulators which are developed with different languages and platforms. Run-Time Infrastructure(RTI) is a software which implements the HLA Interface Specification. With the development of time management service of RTI, it is necessary to consider an efficient design approach and an algorithm of Greatest Available Logical Time(GALT) computation. However, many time management services of existing RTIs have difficulty in modification and extension. Although some RTIs avoid this difficulty through modular design, they comply with not IEEE 1516 HLA/RTI but HLA 1.3. In addition, a lot of RTIs made use of well-known Mattern's algorithm for GALT computation. However, Mattern's algorithm has a few limitations for applying to IEEE 1516 HLA/RTI. This paper proposes a modular design and an implementation of time management service for IEEE 1516 HLA/RTI. We divided th time management service module into two sub-modules: a TIME module and a GALT module and used Mattern's algorithm improved for IEEE 1516 HLARTI. The paper also contains several experimental results in order to evaluate our time management service module.