ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core

  • Received : 2003.01.15
  • Published : 2003.10.31
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Abstract

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

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References

  1. System-on-a-Chip Verification: Methodology and Technique Rashinkar, P.;Paterson, P.;Singh, L.
  2. Reuse Methodology Manual: For System-on-a-Chip Designs Keating, M.;Bricaud, P.
  3. Microprocessor Report v.13 no.17 Brainiacs, Speed Demons, and Farewell Gwennap, L.
  4. Proc. of 6th ACSAC 2001 High-Performance Extendable Instruction Set Computing Lee, H.;Beckett, P.;Appelbe, B.
  5. Proc. of 2nd AP-ASIC 2000 AE32000: An Embedded Microprocessor Core Oh, H.C.;Kim, H.G.;Jung, H.S.;Lee, J.W.;Kim, B.J.;Jung, J.Y.;Min, B.G.;Lim, J.Y.;Lee, H.;Kwon, K.H.
  6. Introduction to Thumb
  7. MIPS16: High-Density MIPS for the Embedded Market Kissell, K.D.
  8. IEEE J. of Solid-State Circuits v.36 no.11 An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications Clark, L.T.;Hoffman, E.J.;Miller, J.;Biyani, M.;Liao, Y.;Strazdus, S.;Morrow, M.;Verlarde, K.E.;Yarch, M.A.
  9. Using Background Debug Mode for the M68HC12 Family Motorola
  10. Verilog Coding Guideline v1.0 SIPAC
  11. Proc. of ICCD-98 Zen and the Art of Alpha Verification Dohm, N.;Ramey, C.;Brown, D.;Hildbrandt, S.;Huggins, J.;Quinn, M.;Taylor, C.
  12. Proc. of 4th COOL Chips C166S V2-A Single Cycle 16-Bit Microcontroller and DSP Core for Next Generation Systems on Chips Maier, K.D.
  13. Synopsis, Version 2000.11 Synopsis Inc.
  14. ETRI J. v.24 no.5 A DSP Architecture for High-Speed FFT in OFDM Systems Lee, J.;Lee, J.;Sunwoo, M.H.;Moh, S.;Oh, S.