• ETRI Journal
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• v.42 no.3
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• pp.376-387
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• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06d
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• pp.360-365
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• 2010

In this paper, we present a distributed algorithm for detecting dynamic event regions in wireless sensor network with the consideration on energy saving. Our model is that the sensing field is monitored by a large number of randomly distributed sensors with low-power battery and limited functionality, and that the event region is dynamic with motion or changing the shape. At any time that the event happens, we need some sensors awake to detect it and to wake up its k-hop neighbors to detect further events. Scheduling for the network to save the total power-cost or to maximize the monitoring time has been studied extensively. Our scheme is that some predetermined sensors, called critical sensors are awake all the time and when the event is detected by a critical sensor the sensor broadcasts to the neighbors to check their sensing area. Then the neighbors check their area and decide whether they wake up or remain in sleeping mode with certain criteria. Our algorithm uses only 2 bit of information in communication between sensors, thus the total communication cost is low, and the speed of detecting all event region is high. We adapt two kinds of measure for the wake-up decision. With suitable threshold values, our algorithm can be applied for many applications and for the trade-off between energy saving and the efficiency of event detection.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.257-260
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• 2001

Buffers, on which much research is being done, are being used as a means to alleviate impacts in processes. Impacts occur from variation which is caused by uncertainty. Current buffers just accept variation as it comes and have just been used as a means to reduce impact. The purpose of this research try to understand the assorted variations which arise from limited resources and information and then we present a division of buffers as the way to overcome these variations. Through the process of dividing buffers into screening buffers, pulling buffers, shielding buffers, and working buffers, we try to make the process more compact, eliminate unnecessary reduction, speed up the decision making process by excluding excessive information, and improve the reliability of work.

• Journal of the Korea Society for Simulation
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• v.16 no.3
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• pp.1-9
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• 2007

Travel time between two points depends upon whether it is a rush hour or not in metropolitan area. It is true that there is big differences on the time required to get through the area whether going in busy morning or near noon. Another issue is that there exist many delivery points which closely located each other; so no need to consider traveling hours among these points. We designed an efficient procedure to reduce the complexity by considering closely located delivery points as one big delivery point. A computer simulation model is constructed for comparison purposes of the developed heuristic with the optimum solution.

• International Journal of Control, Automation, and Systems
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• v.2 no.3
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• pp.279-288
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• 2004

This paper presents a novel design for a tubular linear brushless permanent-magnet motor. In this design, the magnets in the moving part are oriented in an NS-NS―SN-SN fashion which leads to higher magnetic force near the like-pole region. An analytical methodology to calculate the motor force and to size the actuator was developed. The linear motor is operated in conjunction with a position sensor, three power amplifiers, and a controller to form a complete solution for controlled precision actuation. Real-time digital controllers enhanced the dynamic performance of the motor, and gain scheduling reduced the effects of a nonlinear dead band. In its current state, the motor has a rise time of 30 ms, a settling time of 60 ms, and 25% overshoot to a 5-mm step command. The motor has a maximum speed of 1.5 m/s and acceleration up to 10 g. It has a 10-cm travel range and 26-N maximum pull-out force. The compact size of the motor suggests it could be used in robotic applications requiring moderate force and precision, such as robotic-gripper positioning or actuation. The moving part of the motor can extend significantly beyond its fixed support base. This reaching ability makes it useful in applications requiring a small, direct-drive actuator, which is required to extend into a spatially constrained environment.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.6
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.171-182
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• 2003

In this paper, we propose an efficient and simple fair queueing algorithm, called Minimum Possible Virtual Start Time Fair Queueing (MPSFQ), which has O(1) complexity for the virtual time computation while it has good delay and fairness properties. The key idea of MPSFQ is that it has an easy system virtual time recalibration method while it follows a rate-proportional property. MPSFQ algorithm recalibrates system virtual time to the minimum possible virtual start time of all backlogged sessions. We will show our algorithm has good delay and fairness properties by analysis.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1781-1787
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• 1997

Future high speed networks are expected to use the Asynchronous Transfer Mode(ATM), which provides desired quality of service for the various traffic types(e.g., voice, video and data). Proper traffic control scheme helps ensure efficient and fair operation of networks. In this paper, we analyze various related traffic-control strategies and propose a new traffic control scheme and ATM control architecture with an integrated buffer management method and multi-thresholds in order to solve the problem of each class's cell loss ratio and cell delay in ATM networks. In addition, we evaluate the performance improvement of the proposed traffic control scheme through simulation. As shown in the result, the proposed traffic control scheme improves cell loss ratio in proportion to the buffer size.