• The Transactions of the Korea Information Processing Society
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• v.13 no.7
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• pp.311-318
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• 2024

As the amount of data increases due to the development of artificial intelligence and the Internet, data management is becoming increasingly important, and the efficient utilization of data retrieval and memory space is crucial. In this study, we investigate how to optimize search speed and memory efficiency by analyzing data structure based on metadata. As a research method, we compared and analyzed the performance of the array, association list, dictionary binary tree, and graph data structures using metadata of photographic images, focusing on temporal and space complexity. Through experimentation, it was confirmed that dictionary data structure performs best in collection speed and graph data structure performs best in search speed when dealing with large-scale image data. We expect the results of this paper to provide practical guidelines for selecting data structures to optimize search speed and memory efficiency for the images data.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.491-492
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• 2008

According to high-speed large scale integration trend of Memory module product, many type of noises, such a reflection, cross-talk simultaneous switching noise, occur on the Package PCB and they make the deterioration of memory module's performance and reliability. As module products have more high efficiency, Hardware of test board and socket has to be considered In test of the high-speed Memory Module. we mainly focused on improvement of Signal integrity Using the High Frequency Test socket that we invented

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.133-136
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• 2000

A RVLC(Reversible Variable Length Code) with an efficient table memory is proposed in this paper. In the conventional decoding methods, the weight of symbols and code values are used for the decoding table. These methods can be applied for Huffman decoding. In VLC decoding, many studies have been done for memory efficiency and decoding speed. We propose an improved table construction method for general VLC and RVLC decoding, which uses the transition number of bits within a symbol with an enhanced weight decomposition. In this method, tile table for RVLC decoding can be implemented with a smaller memory

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.215-216
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• 2008

Ultra wideband (UWB) system is one of the promising solutions for future short-range communication which has recently received a great attention by many researchers. In this paper, we proposed 128-point low power FFT structure based on the memory for UWB systems. The proposed structure can improve implementation area and power consumption efficiency as it consists of one of the butterfly PE and a little memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.801-804
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• 2009

In this paper, the Linux kernel memory map was analyzed as the approach to Improving performance for Embedded Linux system. Since the Linux kernel memory map supporting a stability and various H/W platforms and in which it becomes to the general purpose system with optimization manages the role of being important in the booting time and the efficient system utilization of resources, the analysis of the kernel memory map is required for the performance improvement of the Embedded Linux system in which it is restrictive the resources. According to the analysis result, and of the Linux kernel memory, the booting speed of and improvement of the memory efficiency were confirmed. It is therefore considered that the proposed in this paper and kernel memory allocation method are suitable to the memory availability improvement of the Embedded Linux system.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.635-642
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• 2003

The radical development of recent network technology provides the basic foundation which can establish a high speed and cheap cluster system. It is a general trend that conventional cluster systems are built as the system over a fixed level based on stabilized and high speed local networks. A multi-distributed web cluster group is a web cluster model which can obtain high performance, high efficiency and high availability through mutual cooperative works between effective job division and system nodes through parallel performance of a given work and shared memory of SC-Server with low price and low speed system nodes on networks. For this, multi-distributed web cluster group builds a sub-cluster group bound with single imaginary networks of multiple system nodes and uses the web distributed shared memory of system nodes for the effective data transmission within sub-cluster groups. Since the presented model uses a load balancing and parallel computing method of large-scale work required from users, it can maximize the processing efficiency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.51-61
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• 2008

This paper suggests a new way to implement high speed AES on Intel Core2 processors and AMD Athlon64 processors, which are used all over the world today. First, Core2 Processors of EM64T architecture's memory-access-instruction processing efficiency are lower than calculus-instruction processing efficiency. So, previous AES implementation techniques, which had a high rate of memory-access-instruction, could cause memory-bottleneck. To improve this problem we present the partial round key techniques that reduce the rate of memory-access-instruction. The result in Intel Core2Duo 3.0 Ghz Processors show 185 cycles/block and 2.0 Gbps's throughputs in ECB mode. This is 35 cycles/block faster than bernstein software, which is known for being the fastest way. On the other side, in AMD64 processors of AMD64 architecture, by removing bottlenecks that occur in decoding processing we could improve the speed, with the result that the Athlon64 processor reached 170 cycles/block. The result that we present is the same performance of Matsui's unpublished software.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1353-1360
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• 2016

We analyze the efficiency of the double-block-length hash functions, Abreast-DM, HIROSE, MDC-2, MJH, MJH-Double based on AES or LEA. We use optimized open-source code for AES, and our implemented source code for LEA. As a result, the hash functions based on LEA are generally more efficient than those, based on AES. In terms of speed, the hash function with LEA are 6%~19% faster than those with AES except for Abreast-DM. In terms of memory, the hash functions with LEA has 20~30 times more efficient than those with AES.