• Electrical & Electronic Materials
• /
• v.10 no.8
• /
• pp.783-793
• /
• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.59-62
• /
• 2000

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.33 no.5
• /
• pp.427-431
• /
• 2020

In this research, we evaluated the electrical properties of polycrystalline-gallium-oxIde (Ga₂O₃) thin films grown by mist-CVD. A 500~800 nm-thick Ga₂O₃ film was used as a channel in a fabricated bottom-gate MOSFET device. The phase stability of the β-phase Ga₂O₃ layer was enhanced by an annealing treatment. A Ti/Al metal stack served as source and drain electrodes. Maximum drain current (I_D) exceeded 1 mA at a drain voltage (V_D) of 20 V. Electron mobility of the β-Ga₂O₃ channel was determined from maximum transconductance (g_m), as approximately, 1.39 ㎠/Vs. Reasonable device characteristics were demonstrated, from measurement of drain current-gate voltage, for mist-CVD-grown Ga₂O₃ thin films.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.1-7
• /
• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.525-536
• /
• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.10
• /
• pp.763-766
• /
• 2010

By improving the conducting process of metal source/drain (S/D) in direct contact with the channel, schottky barrier metal-oxide-semiconductor field effect transistors (SB MOSFETs) reveal low extrinsic parasitic resistances, offer easy processing and allow for well-defined device geometries down to the smallest dimensions. In this work, we investigated the arrhenius plots of the SB MOSFETs with different S/D schottky barrier (SB) heights between simulated and experimental current-voltage characteristics. We fabricated SB MOSFETs using difference S/D metals such as Cr (${\Phi}_{Cr}$ ~4.5 eV) and Ni (${\Phi}_{Ni}$~5.2 eV), respectively. Schottky barrier height (${\Phi}_B$) of the fabricated devices were measured to be 0.25~0.31 eV (Cr-S/D device) and 0.16~0.18 eV (Ni-S/D device), respectively in the temperature range of 300 K and 475 K. The experimental results have been compared with 2-dimensional simulations, which allowed bandgap diagram analysis.

• Journal of Information Display
• /
• v.10 no.3
• /
• pp.131-136
• /
• 2009

This is a report on the fabrication of a flexible OTFT backplane for electrophoretic display (EPD) using a printing technology. A practical printing technology for a polycarbonate substrate was developed by combining the conventional screen and inkjet printing technologies with the wet etching and oxygen plasma processes. For the gate electrode, the screen printing technology with Ag ink was developed to define the minimum line width of ${\sim}5{\mu}m$ and the thickness of ${\sim}70nm$ with the resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, which are suitable for displays with SVGA resolution. For the source and drain (S/D) electrodes, PEDOT:PSS, whose conductivity was drastically enhanced to 450 S/cm by adding 10 wt% glycerol, was adopted. In addition, the modified PEDOT:PSS could be neatly confined in the specific S/D electrode area that had been pretreated with oxygen. The OTFTs that made use of the developed printing technology produced a mobility of ${\sim}0.13cm^2/Vs.ec$ and an on/off current ratio of ${\sim}10^6$, which are comparable to those using thermally evaporated Au for the S/D electrode.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.4
• /
• pp.77-85
• /
• 1999

By assuming a linearly graded depletion edge approximation in the intrinsic MOS region and by taking into account the mobility variation dependent on both lateral and vertical fields, a physics-based analytical model for a short-channel(n-channel) MOSFET is suggested. Derived expressions for the threshold voltage and the drain current of typical MOSFET is structures could be used in a unified manner for all operating range. The threshold voltage was calculated by changing following variables : channel length, drain-source voltage, source-substrate voltage, p-substrate doping level, and oxide thickness. It is shown that the threshold voltage decreases almost exponentially as the channel length decreases. In addition, the short-channel threshold voltage roll-off, the channel length modulation and the electron mobility degradation can be derived within a satisfactory accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.887-890
• /
• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of Convergence for Information Technology
• /
• v.11 no.11
• /
• pp.159-165
• /
• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.